Redundant column substitution architecture with improved column access
time
    1.
    发明授权
    Redundant column substitution architecture with improved column access time 失效
    冗余列替代架构,具有改进的列访问时间

    公开(公告)号:US4691300A

    公开(公告)日:1987-09-01

    申请号:US811856

    申请日:1985-12-20

    IPC分类号: G11C29/00 G11C13/00

    CPC分类号: G11C29/846

    摘要: An apparatus and method for redundant column substitution in a memory device with column redundancy. Rather than inhibiting normal column decoding and selecting in response to a defective column address, the present invention proceeds in parallel with normal column access and redundant column access. The I/O multiplexer receives both the normal and redundant data and, in response to an input from the redundant column decoder, selects the redundant data. Column access time is improved in the case of substituted redundant columns due to the lack of inhibiting the normal column select process. Redundant columns are located physically close to the I/O multiplexer to provide for shorter I/O lines and further improved access time for the redundant columns. Floating normal bit lines are avoided in this scheme since normal column selection is not inhibited.

    摘要翻译: 具有列冗余的存储器件中的冗余列替换的装置和方法。 本发明与正常的列访问和冗余列访问并行进行,而不是抑制正常列解码和响应于缺陷列地址的选择。 I / O多路复用器接收正常和冗余数据,并且响应于冗余列解码器的输入选择冗余数据。 在取代冗余列的情况下,由于缺乏禁止正常的列选择过程,列存取时间得到改善。 冗余列位于物理上靠近I / O多路复用器,以提供更短的I / O线,并进一步改善冗余列的访问时间。 在该方案中避免了浮动正常位线,因为不禁止正常的列选择。

    Precharge of a dram data line to an intermediate voltage
    2.
    发明授权
    Precharge of a dram data line to an intermediate voltage 失效
    将电视数据线预充电到中间电压

    公开(公告)号:US4740921A

    公开(公告)日:1988-04-26

    申请号:US784450

    申请日:1985-10-04

    CPC分类号: G11C11/4094 G11C11/4096

    摘要: A dynamic random access memory has data line pair which receives data from a selected pair of bit lines. Coupled to the data line pair is a secondary amplifier for amplifying the data provided to the data line pair from the bit line pair. The secondary amplifier has a maximum gain when the inputs are at a voltage intermediate a power supply voltage. Prior to the pair of bit lines being coupled to the data line pair, the data lines are biased to the intermediate voltage which is in the range of maximum gain of the secondary amplifier so that the secondary amplifier will operate at maximum gain which results in increased speed of operation of the dynamic random access memory.

    摘要翻译: 动态随机存取存储器具有数据线对,其从选定的位线对接收数据。 耦合到数据线对的是用于放大从位线对提供给数据线对的数据的次级放大器。 当输入处于电源电压以上的电压时,次级放大器具有最大增益。 在一对位线耦合到数据线对之前,数据线被偏置到在次级放大器的最大增益范围内的中间电压,使得次级放大器将以最大增益工作,这导致增加 动态随机存取存储器的运行速度。