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    Virtual memory address translation mechanism with controlled data persistence
    3.
    发明授权
    Virtual memory address translation mechanism with controlled data persistence 失效

    公开(公告)号：US4638426A

    公开(公告)日：1987-01-20

    申请号：US573975

    申请日：1983-09-19

    申请人： Albert Chang ,  John Cocke ,  Mark F. Mergen ,  George Radin

    发明人： Albert Chang ,  John Cocke ,  Mark F. Mergen ,  George Radin

    IPC分类号： G06F13/00 ,  G06F11/07 ,  G06F12/00 ,  G06F12/10 ,  G06F12/14

    CPC分类号： G06F11/0772 ,  G06F11/073 ,  G06F11/0781 ,  G06F12/1036 ,  G06F12/1475

    摘要： A memory address translation and related control system for performing the dual functions of converting virtual memory addresses generated by the CPU into real memory addresses in a highly efficient and versatile manner and for controlling certain memory functions such as journalling. The address translation function comprises two steps, the first comprising converting the virtual address into a second virtual address or an effective address and finally the step of converting the effective address into a real memory address. The first step utilizes a set of special registers addressable by a small field to the CPU generated virtual address which converts the virtual address into an expanded form. The second or effective address is then used as the subject of the second or address translation step. To greatly enhance the translation of frequently used virtual addresses, a special set of translation tables referred to herein as a Translation Look-Aside, Buffer (TLB) contain current effective to real address translations for use where frequently referenced addresses are requested. The TLBs are addressed using a subset of the effective address whereupon the contents of the addressed TLB is examined for a match with the effective address. If the addresses match a successful address translation is possible and the real address stored in the address field of the TLB is available for system use. If the desired effective address is not present in the TLB, the page frame tables stored in main memory are accessed and searched for the desired effective address and if found the associated real address is accessed. Further a special data field is provided in both the TLBs and the page frame tables in main memory wherein a bit is provided for each line in the referenced page at a given effective to real address translation which bits may be used to indicate when a line of data has been accessed or altered.

    Virtual memory address translation mechanism with controlled data persistence
    4.
    再颁专利
    Virtual memory address translation mechanism with controlled data persistence 失效
    具有受控数据持久性的虚拟内存地址转换机制

    公开(公告)号：USRE37305E1

    公开(公告)日：2001-07-31

    申请号：US07812837

    申请日：1991-12-20

    申请人： Albert Chang ,  John Cocke ,  Mark F. Mergen ,  George Radin

    发明人： Albert Chang ,  John Cocke ,  Mark F. Mergen ,  George Radin

    IPC分类号： G06F1210

    CPC分类号： G06F11/0772 ,  G06F11/073 ,  G06F11/0781 ,  G06F12/1036 ,  G06F12/1475 ,  G06F2212/683

    摘要： A memory address translation and related control system for performing the dual functions of converting virtual memory addresses generated by the CPU into real memory addresses in a highly efficient and versatile manner and for controlling certain memory functions such as journalling. The address translation function comprises two steps, the first comprising converting the virtual address into a second virtual address or an effective address and finally the step of converting the effective address into a real memory address. The first step utilizes a set of special registers addressable by a small field to the CPU generated virtual address which converts the virtual address into an expanded form. The second or effective address is then used as the subject of the second or address translation step. To greatly enhance the translation of frequently used virtual addresses, a special set of translation tables referred to herein as a Translation Look-Aside, Buffer (TLB) contain current effective to real address translations for use where frequently referenced addresses are requested. The TLBs are addressed using a subset of the effective address whereupon the contents of the addressed TLB is examined for a match with the effective address. If the addresses match a successful address translation is possible and the real address stored in the address field of the TLB is available for system use. If the desired effective address is not present in the TLB, the page frame tables stored in main memory are accessed and searched for the desired effective address and if found the associated real address is accessed. Further a special data field is provided in both the TLBs and the page frame tables in main memory wherein a bit is provided for each line in the referenced page at a given effective to real address translation which bits may be used to indicate when a line of data has been accessed or altered.

    摘要翻译： 一种存储器地址转换和相关控制系统，用于执行将由CPU产生的虚拟存储器地址以高效和通用的方式转换为实际存储器地址并用于控制某些存储器功能（例如日志记录）的双重功能。 地址转换功能包括两个步骤，第一步包括将虚拟地址转换为第二虚拟地址或有效地址，最后将有效地址转换成实际存储器地址的步骤。 第一步使用一组可由小字段寻址的特殊寄存器到CPU生成的虚拟地址，将虚拟地址转换为扩展形式。 然后将第二或有效地址用作第二或地址转换步骤的主题。 为了极大地增强频繁使用的虚拟地址的翻译，在本文中称为翻译旁边的特殊的一组转换表，缓冲器（TLB）包含当前有效的实际地址转换，以供请求经常被引用的地址使用。 使用有效地址的子集寻址TLB，由此检查寻址的TLB的内容以与有效地址的匹配。 如果地址匹配成功的地址转换是可能的，并且存储在TLB的地址字段中的真实地址可用于系统使用。 如果TLB中不存在期望的有效地址，则存储在主存储器中的页框表被访问并搜索期望的有效地址，并且如果找到，则访问相关联的实际地址。 此外，在主存储器中的TLB和页面帧表中都提供了特殊数据字段，其中在给定的有效到实际地址转换中为参考页面中的每一行提供一个位，哪些位可以用于指示何时一行 数据已被访问或更改。

    Secure recursive virtualization
    7.
    发明授权
    Secure recursive virtualization 失效
    安全的递归虚拟化

    公开(公告)号：US08286164B2

    公开(公告)日：2012-10-09

    申请号：US12537808

    申请日：2009-08-07

    申请人： William E. Hall ,  Guerney D. H. Hunt ,  Paul A. Karger ,  Suzanne K. McIntosh ,  Mark F. Mergen ,  David R. Safford ,  David C. Toll

    发明人： William E. Hall ,  Guerney D. H. Hunt ,  Paul A. Karger ,  Suzanne K. McIntosh ,  Mark F. Mergen ,  David R. Safford ,  David C. Toll

    IPC分类号： G06F9/455 ,  G06F21/00

    CPC分类号： G06F9/45533 ,  G06F9/5077 ,  G06F21/57 ,  G06F2009/4557 ,  G06F2009/45579

    摘要： A mechanism is provided for performing secure recursive virtualization of a computer system. A portion of memory is allocated by a virtual machine monitor (VMM) or an operating system (OS) to a new domain. An initial program for the new domain is loaded into the portion of memory. Secure recursive virtualization firmware (SVF) in the data processing system is called to request that the new domain be generated. A determination is made as to whether the call is from a privileged domain or a non-privileged domain. Responsive to the request being from a privileged domain, all access to the new domain is removed from any other domain in the data processing system. Responsive to receiving an indication that the new domain has been generated, an execution of the initial program is scheduled.

    摘要翻译： 提供了一种用于执行计算机系统的安全递归虚拟化的机制。 内存的一部分由虚拟机监视器（VMM）或操作系统（OS）分配给新域。 新域的初始程序被加载到内存部分。 调用数据处理系统中的安全递归虚拟化固件（SVF）来请求生成新的域。 确定呼叫是来自特权域还是非特权域。 响应于来自特权域的请求，对数据处理系统中的任何其他域的所有对新域的访问都将被删除。 响应于接收到新域已被生成的指示，调度初始程序的执行。

    Logical Partition Memory
    9.
    发明申请
    Logical Partition Memory 有权
    逻辑分区内存

    公开(公告)号：US20100125709A1

    公开(公告)日：2010-05-20

    申请号：US12272261

    申请日：2008-11-17

    申请人： William E. Hall ,  Guerney D.H. Hunt ,  Paul A. Karger ,  Mark F. Mergen ,  David R. Safford ,  David C. Toll

    发明人： William E. Hall ,  Guerney D.H. Hunt ,  Paul A. Karger ,  Mark F. Mergen ,  David R. Safford ,  David C. Toll

    IPC分类号： G06F12/10 ,  G06F12/00 ,  G06F12/02

    CPC分类号： G06F12/1036

    摘要： A mechanism is provided, in a data processing system, for accessing memory based on an effective address submitted by a process of a partition. The mechanism may translate the effective address into a virtual address using a segment look-aside buffer. The mechanism may further translate the virtual address into a partition real address using a page table. Moreover, the mechanism may translate the partition real address into a system real address using a logical partition real memory map for the partition. The system real address may then be used to access the memory.

    摘要翻译： 在数据处理系统中提供了一种基于由分区的进程提交的有效地址来访问存储器的机制。 该机制可以使用段间隔缓冲区将有效地址转换为虚拟地址。 该机制可以使用页表进一步将虚拟地址转换成分区实际地址。 此外，该机制可以使用分区的逻辑分区实际存储器映射将分区实际地址转换为系统实际地址。 然后可以使用系统实际地址来访问存储器。