公开(公告)号：US4638426A

公开(公告)日：1987-01-20

申请号：US573975

申请日：1983-09-19

申请人： Albert Chang ,  John Cocke ,  Mark F. Mergen ,  George Radin

发明人： Albert Chang ,  John Cocke ,  Mark F. Mergen ,  George Radin

IPC分类号： G06F13/00 ,  G06F11/07 ,  G06F12/00 ,  G06F12/10 ,  G06F12/14

CPC分类号： G06F11/0772 ,  G06F11/073 ,  G06F11/0781 ,  G06F12/1036 ,  G06F12/1475

摘要： A memory address translation and related control system for performing the dual functions of converting virtual memory addresses generated by the CPU into real memory addresses in a highly efficient and versatile manner and for controlling certain memory functions such as journalling. The address translation function comprises two steps, the first comprising converting the virtual address into a second virtual address or an effective address and finally the step of converting the effective address into a real memory address. The first step utilizes a set of special registers addressable by a small field to the CPU generated virtual address which converts the virtual address into an expanded form. The second or effective address is then used as the subject of the second or address translation step. To greatly enhance the translation of frequently used virtual addresses, a special set of translation tables referred to herein as a Translation Look-Aside, Buffer (TLB) contain current effective to real address translations for use where frequently referenced addresses are requested. The TLBs are addressed using a subset of the effective address whereupon the contents of the addressed TLB is examined for a match with the effective address. If the addresses match a successful address translation is possible and the real address stored in the address field of the TLB is available for system use. If the desired effective address is not present in the TLB, the page frame tables stored in main memory are accessed and searched for the desired effective address and if found the associated real address is accessed. Further a special data field is provided in both the TLBs and the page frame tables in main memory wherein a bit is provided for each line in the referenced page at a given effective to real address translation which bits may be used to indicate when a line of data has been accessed or altered.

公开(公告)号：USRE37305E1

公开(公告)日：2001-07-31

申请号：US07812837

申请日：1991-12-20

申请人： Albert Chang ,  John Cocke ,  Mark F. Mergen ,  George Radin

发明人： Albert Chang ,  John Cocke ,  Mark F. Mergen ,  George Radin

IPC分类号： G06F1210

CPC分类号： G06F11/0772 ,  G06F11/073 ,  G06F11/0781 ,  G06F12/1036 ,  G06F12/1475 ,  G06F2212/683

摘要： A memory address translation and related control system for performing the dual functions of converting virtual memory addresses generated by the CPU into real memory addresses in a highly efficient and versatile manner and for controlling certain memory functions such as journalling. The address translation function comprises two steps, the first comprising converting the virtual address into a second virtual address or an effective address and finally the step of converting the effective address into a real memory address. The first step utilizes a set of special registers addressable by a small field to the CPU generated virtual address which converts the virtual address into an expanded form. The second or effective address is then used as the subject of the second or address translation step. To greatly enhance the translation of frequently used virtual addresses, a special set of translation tables referred to herein as a Translation Look-Aside, Buffer (TLB) contain current effective to real address translations for use where frequently referenced addresses are requested. The TLBs are addressed using a subset of the effective address whereupon the contents of the addressed TLB is examined for a match with the effective address. If the addresses match a successful address translation is possible and the real address stored in the address field of the TLB is available for system use. If the desired effective address is not present in the TLB, the page frame tables stored in main memory are accessed and searched for the desired effective address and if found the associated real address is accessed. Further a special data field is provided in both the TLBs and the page frame tables in main memory wherein a bit is provided for each line in the referenced page at a given effective to real address translation which bits may be used to indicate when a line of data has been accessed or altered.

摘要翻译： 一种存储器地址转换和相关控制系统，用于执行将由CPU产生的虚拟存储器地址以高效和通用的方式转换为实际存储器地址并用于控制某些存储器功能（例如日志记录）的双重功能。 地址转换功能包括两个步骤，第一步包括将虚拟地址转换为第二虚拟地址或有效地址，最后将有效地址转换成实际存储器地址的步骤。 第一步使用一组可由小字段寻址的特殊寄存器到CPU生成的虚拟地址，将虚拟地址转换为扩展形式。 然后将第二或有效地址用作第二或地址转换步骤的主题。 为了极大地增强频繁使用的虚拟地址的翻译，在本文中称为翻译旁边的特殊的一组转换表，缓冲器（TLB）包含当前有效的实际地址转换，以供请求经常被引用的地址使用。 使用有效地址的子集寻址TLB，由此检查寻址的TLB的内容以与有效地址的匹配。 如果地址匹配成功的地址转换是可能的，并且存储在TLB的地址字段中的真实地址可用于系统使用。 如果TLB中不存在期望的有效地址，则存储在主存储器中的页框表被访问并搜索期望的有效地址，并且如果找到，则访问相关联的实际地址。 此外，在主存储器中的TLB和页面帧表中都提供了特殊数据字段，其中在给定的有效到实际地址转换中为参考页面中的每一行提供一个位，哪些位可以用于指示何时一行 数据已被访问或更改。

公开(公告)号：US4937736A

公开(公告)日：1990-06-26

申请号：US126529

申请日：1987-11-30

申请人： Albert Chang ,  John Cocke ,  Mark F. Mergen ,  Richard R. Oehler

发明人： Albert Chang ,  John Cocke ,  Mark F. Mergen ,  Richard R. Oehler

IPC分类号： G06F12/00 ,  G06F12/14

CPC分类号： G06F12/1475

摘要： A method and apparatus for controlling access to data blocks stored by addresses in a memory and concurrently accessible by a plurality of transactions is provided. The method includes the steps of receiving an address of a data block to be accessed by a first transaction, deriving from the address an access table entry corresponding to the data block where the entry includes lock data that governs access to the data block, and providing the access if permitted by the lock data, or providing the access, if not permitted by the lock data, and recording the occurrence of the access in the lock data.

公开(公告)号：US4718008A

公开(公告)日：1988-01-05

申请号：US819459

申请日：1986-01-16

申请人： Albert Chang ,  Mark F. Mergen ,  John T. O'Quin, II ,  John C. O'Quin, III ,  Mark D. Rogers

发明人： Albert Chang ,  Mark F. Mergen ,  John T. O'Quin, II ,  John C. O'Quin, III ,  Mark D. Rogers

IPC分类号： G06F9/48 ,  G06F12/10 ,  G06F1/00

CPC分类号： G06F9/4812 ,  G06F12/10

摘要： A method to logically serialize a plurality of independent system events in a virtual memory data processing system. Each event causes interrupt servicing routines to be executed and requires data structures that record the status of virtual pages to be updated. The system events include the interrupt that is generated as a result of a page fault, the interrupt that is generated as a result of a paging I/O completion operation that resolves a page fault, and lastly interrupts generated in response to a supervisory call to a paging service.

摘要翻译： 一种在虚拟存储器数据处理系统中逻辑地串行化多个独立系统事件的方法。 每个事件都会导致中断服务程序被执行，并且需要记录要更新的虚拟页面状态的数据结构。 系统事件包括作为页面错误的结果而产生的中断，作为解决页面错误的分页I / O完成操作而产生的中断，以及最后响应于监视调用生成的中断 寻呼服务。

公开(公告)号：USRE36462E

公开(公告)日：1999-12-21

申请号：US726565

申请日：1996-10-04

申请人： Albert Chang ,  Mark F. Mergen ,  John T. O'Quin, II ,  John C. O'Quin, III ,  Mark D. Rogers

发明人： Albert Chang ,  Mark F. Mergen ,  John T. O'Quin, II ,  John C. O'Quin, III ,  Mark D. Rogers

IPC分类号： G06F9/00 ,  G06F12/00 ,  G06F12/10

CPC分类号： G06F12/10

摘要： A method to logically serialize a plurality of independent system events in a virtual memory data processing system. Each event causes interrupt servicing routines to be executed and requires data structures that record the status of virtual pages to be updated. The system events include the interrupt that is generated as a result of a page fault, the interrupt that is generated as a result of a paging I/O completion operation that resolves a page fault, and lastly interrupts generated in response to a supervisory call to a paging service.

摘要翻译： 一种在虚拟存储器数据处理系统中逻辑地串行化多个独立系统事件的方法。 每个事件都会导致中断服务程序被执行，并且需要记录要更新的虚拟页面状态的数据结构。 系统事件包括作为页面错误的结果而产生的中断，作为解决页面错误的分页I / O完成操作而产生的中断，以及最后响应于监视调用生成的中断 寻呼服务。

公开(公告)号：US20050289289A1

公开(公告)日：2005-12-29

申请号：US10875600

申请日：2004-06-24

申请人： Albert Chang

发明人： Albert Chang

IPC分类号： G06F9/00 ,  G06F12/00 ,  G06F21/00

CPC分类号： G06F21/6218 ,  G06F2221/2143

摘要： In accordance with at least some embodiments of the invention, a system comprises a processor, a non-volatile storage device coupled to the processor, a read-only memory (ROM) coupled to the processor and to the non-volatile storage device, and software stored in the ROM. The software is executable by the processor and configured to erase the non-volatile storage device by overwriting substantially all of the addressable locations of the non-volatile storage device while boot firmware is controlling the system.

摘要翻译： 根据本发明的至少一些实施例，系统包括处理器，耦合到处理器的非易失性存储设备，耦合到处理器和非易失性存储设备的只读存储器（ROM），以及 软件存储在ROM中。 该软件可由处理器执行并且被配置为通过在引导固件正在控制系统的同时覆盖非易失性存储设备的基本上所有可寻址位置来擦除非易失性存储设备。

公开(公告)号：US08612872B2

公开(公告)日：2013-12-17

申请号：US12269388

申请日：2008-11-12

申请人： Albert Chang ,  Shane Gregory Stephens

发明人： Albert Chang ,  Shane Gregory Stephens

IPC分类号： G06F3/048

CPC分类号： G06F3/0481

摘要： A method for providing an animated transition effect between a first display state associated with a first control state of a control element rendered on a graphical user interface of a computer system, and a second display state associated with a second control state of said control element is provided. The method renders the control element in said first state and then receives at the graphic user interface, a user input event to invoke the second control state of the control element. The method evaluates a graph associated with the control element, the graph having entries each corresponding to a state of the control element, each entry comprising an event, an associated transition and a destination state, to identify a graph entry specifying a transition invoked by the input event from a current displayed first state to the destination state, being the second control state. An entry is identified corresponding to the second control state as the current state of the control element and a description of an animation associated with the specified transition is retrieved. The animation is then rendered.

摘要翻译： 用于在与计算机系统的图形用户界面上呈现的控制元素的第一控制状态相关联的第一显示状态与与所述控制元件的第二控制状态相关联的第二显示状态之间提供动画转换效果的方法是： 提供。 该方法使控制元件处于所述第一状态，然后在图形用户界面处接收用户输入事件以调用控制元件的第二控制状态。 该方法评估与控制元素相关联的图形，该图形具有各自对应于控制元素的状态的条目，每个条目包括事件，相关联的转换和目的地状态，以标识指定由所述控制元素调用的转换的图形条目 从当前显示的第一状态到目的地状态的输入事件为第二控制状态。 将对应于第二控制状态的条目识别为控制元件的当前状态，并且检索与指定转换相关联的动画的描述。 然后渲染动画。

公开(公告)号：US08228739B2

公开(公告)日：2012-07-24

申请号：US13184778

申请日：2011-07-18

申请人： Feng Pan ,  Yuxin Wang ,  Jonathan H. Huynh ,  Albert Chang ,  Khin Htoo ,  Qui Vi Nguyen

发明人： Feng Pan ,  Yuxin Wang ,  Jonathan H. Huynh ,  Albert Chang ,  Khin Htoo ,  Qui Vi Nguyen

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C5/147 ,  G11C16/30

摘要： A circuit and corresponding method for providing a reference voltage are presented. The circuit includes a current source having a magnitude with positive temperature correlation connected to a node, and a diode element connected between the node and ground, where the reference voltage is provided from the node. The circuit also includes a variable resistance connected to receive an input indicative of the circuit temperature and through which the diode element is connected to the node. The value of the variable resistance is adjusted based upon the circuit temperature input. The circuit is useful for application as a peripheral circuitry, such as on a flash or other non-volatile memory and other circuits requiring an on-chip reference voltage source.

摘要翻译： 提出了一种用于提供参考电压的电路和相应的方法。 电路包括具有连接到节点的正温度相关幅度的电流源和连接在节点和地之间的二极管元件，其中从该节点提供参考电压。 电路还包括可变电阻，其连接以接收指示电路温度的输入，并且二极管元件通过该电阻连接到节点。 可变电阻的值根据电路温度输入进行调整。 该电路可用作外围电路，例如闪存或其他非易失性存储器以及需要片上参考电压源的其他电路。

公开(公告)号：US07151509B2

公开(公告)日：2006-12-19

申请号：US10746833

申请日：2003-12-24

申请人： Cameron G. Massey ,  Tom F. Reneau ,  Albert Chang

发明人： Cameron G. Massey ,  Tom F. Reneau ,  Albert Chang

IPC分类号： H01Q15/20

CPC分类号： H01Q19/10 ,  H01Q1/362 ,  H01Q11/08 ,  H01Q15/161

摘要： An apparatus and method for use in deploying a wireless communication device is provided that includes an antenna element and a reflector secured proximate a first end of the element. The reflector includes a base, and a flexible wall with a first end positioned proximate the base extending away to a second end positioned about the element. The wall can be deformed from an original position to a deformed position where the second end is temporarily positioned proximate the element and released such that the wall returns to the original position. The method includes deforming the reflector from an original position to an altered position where portions of a rim are proximate the element. The reflector is positioned in contact with the communication device, secured in the altered position, maintained in the altered position with a reduced profile, and released such the reflector elastically returns to the original position.

摘要翻译： 提供了一种用于部署无线通信设备的装置和方法，其包括靠近元件的第一端固定的天线元件和反射器。 反射器包括基部和柔性壁，第一端靠近基部定位，第一端延伸到围绕元件定位的第二端。 壁可以从原始位置变形到变形位置，其中第二端临时定位在元件附近并被释放，使得壁返回到原始位置。 该方法包括将反射器从原始位置变形到轮辋的部分靠近元件的改变位置。 反射器定位成与通信装置接触，固定在改变的位置，以减小的轮廓保持在改变的位置，并且这样的反射器弹性地返回到原始位置。

公开(公告)号：US06948036B2

公开(公告)日：2005-09-20

申请号：US10177274

申请日：2002-06-21

申请人： Thomas W. Grieff ,  James R. Reif ,  Albert Chang

发明人： Thomas W. Grieff ,  James R. Reif ,  Albert Chang

IPC分类号： G06F3/06 ,  G06F11/00 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F3/0659 ,  G06F3/0607 ,  G06F3/0674

摘要： A multi-port adapter and method of operation suitable for use with serial ATA devices is disclosed. An adapter includes a switch that receives input from multiple host devices and an arbiter module for assigning a priority scheme to received commands. An outstanding request table is implemented as a memory module for storing identifying information associated with commands received from multiple host devices, and a free pointers queue is maintained to track slots available in the outstanding request table. A command tracker state machine decodes incoming requests from hosts, monitors the execution by these commands by the ATA device, and updates the memory module to reflect completion of commands. Also disclosed is a storage system including an adapter of the present invention and ATA storage devices.

摘要翻译： 公开了适用于串行ATA设备的多端口适配器和操作方法。 适配器包括从多个主机设备接收输入的交换机和用于向接收到的命令分配优先级方案的仲裁器模块。 一个未完成的请求表被实现为用于存储与从多个主机设备接收的命令相关联的识别信息的存储器模块，并且保持空闲指针队列以跟踪未完成请求表中可用的时隙。 命令跟踪器状态机解码来自主机的传入请求，通过ATA设备监视这些命令的执行，并更新内存模块以反映命令的完成。 还公开了一种包括本发明的适配器和ATA存储设备的存储系统。