公开(公告)号：US07581039B2

公开(公告)日：2009-08-25

申请号：US11179033

申请日：2005-07-11

申请人： Albert Martinez ,  Jean Nicolai

发明人： Albert Martinez ,  Jean Nicolai

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  G06F12/1081

摘要： A method for programming a DMA controller of a system on a chip that includes a CPU, an MMU, and a DMA controller including source, destination, and size registers associated with a base subaddress. In response to a first instruction of a user program that includes a virtual address, the virtual address is translated into a corresponding physical address, and the physical address is stored in a buffer register that is inaccessible to the user program. In response to a second instruction of the user program, the physical address stored in the buffer register is applied to the data bus and a first word including high-order bits indicating the base subaddress is applied to the address bus. The source or destination register is selected according to the first word applied to the address bus and the physical address applied to the data bus is stored in the selected register.

摘要翻译： 一种用于对包括CPU，MMU和DMA控制器的芯片上的系统的DMA控制器进行编程的方法，包括与基本子地址相关联的源，目的地和大小寄存器。 响应于包括虚拟地址的用户程序的第一指令，虚拟地址被转换成对应的物理地址，物理地址存储在用户程序不可访问的缓冲寄存器中。 响应于用户程序的第二指令，存储在缓冲寄存器中的物理地址被施加到数据总线，并且包括指示基本子地址的高位的第一个字被施加到地址总线。 源或目标寄存器根据应用于地址总线的第一个字来选择，并且应用于数据总线的物理地址存储在所选择的寄存器中。

公开(公告)号：US07467239B2

公开(公告)日：2008-12-16

申请号：US11185529

申请日：2005-07-20

申请人： Jean Nicolai ,  Albert Martinez

发明人： Jean Nicolai ,  Albert Martinez

IPC分类号： G06F13/10 ,  G06F13/14

CPC分类号： G06F13/28 ,  G06F12/1081 ,  G06F2213/0038

摘要： A procedure is provided for programming a DMA controller of a system on a chip that includes a CPU, an MMU, a DMA controller including source, destination, and size registers, and entities that are each identified by a physical address and addressable by applying that physical address to the address bus. In response to a first dedicated instruction of a user program, the virtual address is translated into a corresponding physical address, the corresponding physical address is applied to the address bus, a signal having a first value is delivered to the DMA controller, and a signal having a second value is delivered to the entities. When the signal delivered to the DMA controller has the first value, the source register or the destination register of the DMA controller is selected and the corresponding physical address on the address bus is stored in the selected register.

摘要翻译： 提供了一种用于对包括CPU，MMU，包括源，目的地和大小寄存器的DMA控制器的芯片上的系统的DMA控制器进行编程的程序，以及每个由物理地址标识并可通过应用该物理地址来寻址的实体 物理地址到地址总线。 响应于用户程序的第一专用指令，将虚拟地址转换为对应的物理地址，将对应的物理地址应用于地址总线，具有第一值的信号被传送到DMA控制器，并且信号 具有第二个值被传递给实体。 当传送到DMA控制器的信号具有第一个值时，选择DMA控制器的源寄存器或目标寄存器，并将地址总线上相应的物理地址存储在所选寄存器中。

公开(公告)号：US20080155188A1

公开(公告)日：2008-06-26

申请号：US11958958

申请日：2007-12-18

申请人： Stephan Courcambeck ,  Albert Martinez ,  Jean Nicolai ,  William Orlando

发明人： Stephan Courcambeck ,  Albert Martinez ,  Jean Nicolai ,  William Orlando

IPC分类号： G06F9/30 ,  G06F12/02

CPC分类号： G06F12/1483 ,  G06F21/79

摘要： A circuit for controlling the access to at least one area of a memory accessible by a program execution unit, including a first instruction address input; at least one second data address input, the addresses coming from the execution unit; at least one function of correlation of these addresses; and at least one output of a bit for validating the fulfilling of conditions set by the correlation function.

摘要翻译： 一种用于控制对由程序执行单元可访问的存储器的至少一个区域的访问的电路，包括第一指令地址输入; 至少一个第二数据地址输入，来自执行单元的地址; 至少一个这些地址相关的功能; 以及用于验证由相关函数设置的条件的满足的位的至少一个输出。

公开(公告)号：US20060020719A1

公开(公告)日：2006-01-26

申请号：US11179033

申请日：2005-07-11

申请人： Albert Martinez ,  Jean Nicolai

发明人： Albert Martinez ,  Jean Nicolai

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  G06F12/1081

摘要： A method for programming a DMA controller of a system on a chip that includes a CPU, an MMU, and a DMA controller including source, destination, and size registers associated with a base subaddress. In response to a first instruction of a user program that includes a virtual address, the virtual address is translated into a corresponding physical address, and the physical address is stored in a buffer register that is inaccessible to the user program. In response to a second instruction of the user program, the physical address stored in the buffer register is applied to the data bus and a first word including high-order bits indicating the base subaddress is applied to the address bus. The source or destination register is selected according to the first word applied to the address bus and the physical address applied to the data bus is stored in the selected register.

摘要翻译： 一种用于对包括CPU，MMU和DMA控制器的芯片上的系统的DMA控制器进行编程的方法，包括与基本子地址相关联的源，目的地和大小寄存器。 响应于包括虚拟地址的用户程序的第一指令，虚拟地址被转换成对应的物理地址，物理地址存储在用户程序不可访问的缓冲寄存器中。 响应于用户程序的第二指令，存储在缓冲寄存器中的物理地址被施加到数据总线，并且包括指示基本子地址的高位的第一个字被施加到地址总线。 源或目标寄存器根据应用于地址总线的第一个字来选择，并且应用于数据总线的物理地址存储在所选择的寄存器中。

公开(公告)号：US08782367B2

公开(公告)日：2014-07-15

申请号：US11958958

申请日：2007-12-18

申请人： Stéphan Courcambeck ,  Albert Martinez ,  Jean Nicolai ,  William Orlando

发明人： Stéphan Courcambeck ,  Albert Martinez ,  Jean Nicolai ,  William Orlando

IPC分类号： G06F12/00

CPC分类号： G06F12/1483 ,  G06F21/79

摘要： A circuit for controlling the access to at least one area of a memory accessible by a program execution unit, including a first instruction address input; at least one second data address input, the addresses coming from the execution unit; at least one function of correlation of these addresses; and at least one output of a bit for validating the fulfilling of conditions set by the correlation function.

摘要翻译： 一种用于控制对由程序执行单元可访问的存储器的至少一个区域的访问的电路，包括第一指令地址输入; 至少一个第二数据地址输入，来自执行单元的地址; 至少一个这些地址相关的功能; 以及用于验证由相关函数设置的条件的满足的位的至少一个输出。

公开(公告)号：US07337300B2

公开(公告)日：2008-02-26

申请号：US11154281

申请日：2005-06-16

申请人： Daniele Fronte ,  Jean Nicolai ,  Albert Martinez

发明人： Daniele Fronte ,  Jean Nicolai ,  Albert Martinez

IPC分类号： G06F9/34 ,  G06F9/26 ,  G06F12/00

CPC分类号： G06F13/28

摘要： A method is provided for processing a virtual address for a program requesting a DMA transfer. The program is designed to be run in user mode on a system on a chip that includes a central processing unit, a memory management unit, and a DMA controller. The virtual address is a source virtual address or a destination virtual address and has a size of N bits. According to the method, the virtual address is divided into at least two fields of bits. For each of the fields, there is created an N-bit address word comprising a prefix having a given value associated with the field and having more than 1 bit, and the field. The DMA controller is programmed using multiple store instructions that include one store instruction relating to each of the address words created.

摘要翻译： 提供了一种用于处理请求DMA传输的程序的虚拟地址的方法。 该程序被设计为在包括中央处理单元，存储器管理单元和DMA控制器的芯片上的系统上以用户模式运行。 虚拟地址是源虚拟地址或目标虚拟地址，并且具有N位的大小。 根据该方法，虚拟地址被分成至少两个比特字段。 对于每个字段，创建了包括具有与该字段相关联并具有多于1位的给定值的前缀的N位地址字和该字段。 使用多个存储指令对DMA控制器进行编程，其中包括与创建的每个地址字相关的一个存储指令。

公开(公告)号：US20060026311A1

公开(公告)日：2006-02-02

申请号：US11185529

申请日：2005-07-20

申请人： Jean Nicolai ,  Albert Martinez

发明人： Jean Nicolai ,  Albert Martinez

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  G06F12/1081 ,  G06F2213/0038

摘要： A procedure is provided for programming a DMA controller of a system on a chip that includes a CPU, an MMU, a DMA controller including source, destination, and size registers, and entities that are each identified by a physical address and addressable by applying that physical address to the address bus. In response to a first dedicated instruction of a user program, the virtual address is translated into a corresponding physical address, the corresponding physical address is applied to the address bus, a signal having a first value is delivered to the DMA controller, and a signal having a second value is delivered to the entities. When the signal delivered to the DMA controller has the first value, the source register or the destination register of the DMA controller is selected and the corresponding physical address on the address bus is stored in the selected register.

摘要翻译： 提供了一种用于对包括CPU，MMU，包括源，目的地和大小寄存器的DMA控制器的芯片上的系统的DMA控制器进行编程的程序，以及每个由物理地址标识并可通过应用该物理地址来寻址的实体 物理地址到地址总线。 响应于用户程序的第一专用指令，将虚拟地址转换为对应的物理地址，将对应的物理地址应用于地址总线，具有第一值的信号被传送到DMA控制器，并且信号 具有第二个值被传递给实体。 当传送到DMA控制器的信号具有第一个值时，选择DMA控制器的源寄存器或目标寄存器，并将地址总线上相应的物理地址存储在所选寄存器中。

公开(公告)号：US20060010262A1

公开(公告)日：2006-01-12

申请号：US11154281

申请日：2005-06-16

申请人： Daniele Fronte ,  Jean Nicolai ,  Albert Martinez

发明人： Daniele Fronte ,  Jean Nicolai ,  Albert Martinez

IPC分类号： G06F13/28 ,  G06F12/08

CPC分类号： G06F13/28

摘要： A method is provided for processing a virtual address for a program requesting a DMA transfer. The program is designed to be run in user mode on a system on a chip that includes a central processing unit, a memory management unit, and a DMA controller. The virtual address is a source virtual address or a destination virtual address and has a size of N bits. According to the method, the virtual address is divided into at least two fields of bits. For each of the fields, there is created an N-bit address word comprising a prefix having a given value associated with the field and having more than 1 bit, and the field. The DMA controller is programmed using multiple store instructions that include one store instruction relating to each of the address words created.

摘要翻译： 提供了一种用于处理请求DMA传输的程序的虚拟地址的方法。 该程序被设计为在包括中央处理单元，存储器管理单元和DMA控制器的芯片上的系统上以用户模式运行。 虚拟地址是源虚拟地址或目标虚拟地址，并且具有N位的大小。 根据该方法，虚拟地址被分成至少两个比特字段。 对于每个字段，创建了包括具有与该字段相关联并具有多于1位的给定值的前缀的N位地址字和该字段。 使用多个存储指令对DMA控制器进行编程，其中包括与创建的每个地址字相关的一个存储指令。

公开(公告)号：US07461232B2

公开(公告)日：2008-12-02

申请号：US11440706

申请日：2006-05-24

申请人： Jean Nicolai

发明人： Jean Nicolai

IPC分类号： G06F12/10

CPC分类号： G06F12/1036 ,  G06F2212/681 ,  Y02D10/13

摘要： A translation look-aside buffer that stores address translations each of which associate a VPN with a PPN, and which are usable in a first mode of operation of a processor incorporating the buffer for accessing data stored in physical memory. Each entry in the buffer includes a first field for storing the VPN, a second field for storing an intermediate address portion IPN, and a third field for storing the PPN. The first field and the third field are mutually associated via the second field. The buffer is addressable in the first mode of operation of the processor by the content of the first fields. In response to a request for access to eternal memory, it outputs the PPN stored in the third field of a given entry when it is addressed by an input value corresponding to the VPN stored in the first field of said entry.

摘要翻译： 一种翻译后备缓冲器，其存储每个将VPN与PPN相关联的地址转换，并且可以在包含用于访问存储在物理存储器中的数据的缓冲器的处理器的第一操作模式中使用。 缓冲器中的每个条目包括用于存储VPN的第一字段，用于存储中间地址部分IPN的第二字段和用于存储PPN的第三字段。 第一个字段和第三个字段通过第二个字段相互关联。 缓冲器可以通过第一场的内容在处理器的第一操作模式下寻址。 响应于访问永久存储器的请求，当通过与存储在所述条目的第一字段中的VPN相对应的输入值来寻址存储在给定条目的第三字段中的PPN。

公开(公告)号：US20060271760A1

公开(公告)日：2006-11-30

申请号：US11440706

申请日：2006-05-24

申请人： Jean Nicolai

发明人： Jean Nicolai

IPC分类号： G06F12/00

CPC分类号： G06F12/1036 ,  G06F2212/681 ,  Y02D10/13

摘要： A translation look-aside buffer that stores address translations each of which associate a VPN with a PPN, and which are usable in a first mode of operation of a processor incorporating the buffer for accessing data stored in physical memory. Each entry in the buffer includes a first field for storing the VPN, a second field for storing an intermediate address portion IPN, and a third field for storing the PPN. The first field and the third field are mutually associated via the second field. The buffer is addressable in the first mode of operation of the processor by the content of the first fields. In response to a request for access to eternal memory, it outputs the PPN stored in the third field of a given entry when it is addressed by an input value corresponding to the VPN stored in the first field of said entry.

摘要翻译： 一种翻译后备缓冲器，其存储每个将VPN与PPN相关联的地址转换，并且可以在包含用于访问存储在物理存储器中的数据的缓冲器的处理器的第一操作模式中使用。 缓冲器中的每个条目包括用于存储VPN的第一字段，用于存储中间地址部分IPN的第二字段和用于存储PPN的第三字段。 第一个字段和第三个字段通过第二个字段相互关联。 缓冲器可以通过第一场的内容在处理器的第一操作模式下寻址。 响应于访问永久存储器的请求，当通过与存储在所述条目的第一字段中的VPN相对应的输入值来寻址存储在给定条目的第三字段中的PPN。