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    Procedure and device for programming a DMA controller in which a translated physical address is stored in a buffer register of the address processing unit and then applied to the data bus and stored in a register of the DMA controller
    1.
    发明授权
    Procedure and device for programming a DMA controller in which a translated physical address is stored in a buffer register of the address processing unit and then applied to the data bus and stored in a register of the DMA controller 有权
    用于对DMA控制器进行编程的程序和设备，其中翻译的物理地址存储在地址处理单元的缓冲寄存器中，然后施加到数据总线并存储在DMA控制器的寄存器中

    公开(公告)号：US07581039B2

    公开(公告)日：2009-08-25

    申请号：US11179033

    申请日：2005-07-11

    申请人： Albert Martinez ,  Jean Nicolai

    发明人： Albert Martinez ,  Jean Nicolai

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28 ,  G06F12/1081

    摘要： A method for programming a DMA controller of a system on a chip that includes a CPU, an MMU, and a DMA controller including source, destination, and size registers associated with a base subaddress. In response to a first instruction of a user program that includes a virtual address, the virtual address is translated into a corresponding physical address, and the physical address is stored in a buffer register that is inaccessible to the user program. In response to a second instruction of the user program, the physical address stored in the buffer register is applied to the data bus and a first word including high-order bits indicating the base subaddress is applied to the address bus. The source or destination register is selected according to the first word applied to the address bus and the physical address applied to the data bus is stored in the selected register.

    摘要翻译： 一种用于对包括CPU，MMU和DMA控制器的芯片上的系统的DMA控制器进行编程的方法，包括与基本子地址相关联的源，目的地和大小寄存器。 响应于包括虚拟地址的用户程序的第一指令，虚拟地址被转换成对应的物理地址，物理地址存储在用户程序不可访问的缓冲寄存器中。 响应于用户程序的第二指令，存储在缓冲寄存器中的物理地址被施加到数据总线，并且包括指示基本子地址的高位的第一个字被施加到地址总线。 源或目标寄存器根据应用于地址总线的第一个字来选择，并且应用于数据总线的物理地址存储在所选择的寄存器中。

    Method and system for programming a DMA controller in a system on a chip, with the DMA controller having source, destination, and size registers
    2.
    发明授权
    Method and system for programming a DMA controller in a system on a chip, with the DMA controller having source, destination, and size registers 有权
    用于在芯片上的系统中对DMA控制器进行编程的方法和系统，其中DMA控制器具有源，目的地和大小寄存器

    公开(公告)号：US07467239B2

    公开(公告)日：2008-12-16

    申请号：US11185529

    申请日：2005-07-20

    申请人： Jean Nicolai ,  Albert Martinez

    发明人： Jean Nicolai ,  Albert Martinez

    IPC分类号： G06F13/10 ,  G06F13/14

    CPC分类号： G06F13/28 ,  G06F12/1081 ,  G06F2213/0038

    摘要： A procedure is provided for programming a DMA controller of a system on a chip that includes a CPU, an MMU, a DMA controller including source, destination, and size registers, and entities that are each identified by a physical address and addressable by applying that physical address to the address bus. In response to a first dedicated instruction of a user program, the virtual address is translated into a corresponding physical address, the corresponding physical address is applied to the address bus, a signal having a first value is delivered to the DMA controller, and a signal having a second value is delivered to the entities. When the signal delivered to the DMA controller has the first value, the source register or the destination register of the DMA controller is selected and the corresponding physical address on the address bus is stored in the selected register.

    摘要翻译： 提供了一种用于对包括CPU，MMU，包括源，目的地和大小寄存器的DMA控制器的芯片上的系统的DMA控制器进行编程的程序，以及每个由物理地址标识并可通过应用该物理地址来寻址的实体 物理地址到地址总线。 响应于用户程序的第一专用指令，将虚拟地址转换为对应的物理地址，将对应的物理地址应用于地址总线，具有第一值的信号被传送到DMA控制器，并且信号 具有第二个值被传递给实体。 当传送到DMA控制器的信号具有第一个值时，选择DMA控制器的源寄存器或目标寄存器，并将地址总线上相应的物理地址存储在所选寄存器中。

    Translation look-aside buffer supporting mutually untrusted operating systems
    3.
    发明授权
    Translation look-aside buffer supporting mutually untrusted operating systems 有权
    翻译后备缓冲区支持互不信任的操作系统

    公开(公告)号：US07461232B2

    公开(公告)日：2008-12-02

    申请号：US11440706

    申请日：2006-05-24

    申请人： Jean Nicolai

    发明人： Jean Nicolai

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1036 ,  G06F2212/681 ,  Y02D10/13

    摘要： A translation look-aside buffer that stores address translations each of which associate a VPN with a PPN, and which are usable in a first mode of operation of a processor incorporating the buffer for accessing data stored in physical memory. Each entry in the buffer includes a first field for storing the VPN, a second field for storing an intermediate address portion IPN, and a third field for storing the PPN. The first field and the third field are mutually associated via the second field. The buffer is addressable in the first mode of operation of the processor by the content of the first fields. In response to a request for access to eternal memory, it outputs the PPN stored in the third field of a given entry when it is addressed by an input value corresponding to the VPN stored in the first field of said entry.

    摘要翻译： 一种翻译后备缓冲器，其存储每个将VPN与PPN相关联的地址转换，并且可以在包含用于访问存储在物理存储器中的数据的缓冲器的处理器的第一操作模式中使用。 缓冲器中的每个条目包括用于存储VPN的第一字段，用于存储中间地址部分IPN的第二字段和用于存储PPN的第三字段。 第一个字段和第三个字段通过第二个字段相互关联。 缓冲器可以通过第一场的内容在处理器的第一操作模式下寻址。 响应于访问永久存储器的请求，当通过与存储在所述条目的第一字段中的VPN相对应的输入值来寻址存储在给定条目的第三字段中的PPN。

    Translation look-aside buffer
    4.
    发明申请
    Translation look-aside buffer 有权
    翻译后备缓冲区

    公开(公告)号：US20060271760A1

    公开(公告)日：2006-11-30

    申请号：US11440706

    申请日：2006-05-24

    申请人： Jean Nicolai

    发明人： Jean Nicolai

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1036 ,  G06F2212/681 ,  Y02D10/13

    摘要： A translation look-aside buffer that stores address translations each of which associate a VPN with a PPN, and which are usable in a first mode of operation of a processor incorporating the buffer for accessing data stored in physical memory. Each entry in the buffer includes a first field for storing the VPN, a second field for storing an intermediate address portion IPN, and a third field for storing the PPN. The first field and the third field are mutually associated via the second field. The buffer is addressable in the first mode of operation of the processor by the content of the first fields. In response to a request for access to eternal memory, it outputs the PPN stored in the third field of a given entry when it is addressed by an input value corresponding to the VPN stored in the first field of said entry.

    摘要翻译： 一种翻译后备缓冲器，其存储每个将VPN与PPN相关联的地址转换，并且可以在包含用于访问存储在物理存储器中的数据的缓冲器的处理器的第一操作模式中使用。 缓冲器中的每个条目包括用于存储VPN的第一字段，用于存储中间地址部分IPN的第二字段和用于存储PPN的第三字段。 第一个字段和第三个字段通过第二个字段相互关联。 缓冲器可以通过第一场的内容在处理器的第一操作模式下寻址。 响应于访问永久存储器的请求，当通过与存储在所述条目的第一字段中的VPN相对应的输入值来寻址存储在给定条目的第三字段中的PPN。

    Memory area protection circuit
    6.
    发明授权
    Memory area protection circuit 有权
    存储区保护电路

    公开(公告)号：US08782367B2

    公开(公告)日：2014-07-15

    申请号：US11958958

    申请日：2007-12-18

    申请人： Stéphan Courcambeck ,  Albert Martinez ,  Jean Nicolai ,  William Orlando

    发明人： Stéphan Courcambeck ,  Albert Martinez ,  Jean Nicolai ,  William Orlando

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1483 ,  G06F21/79

    摘要： A circuit for controlling the access to at least one area of a memory accessible by a program execution unit, including a first instruction address input; at least one second data address input, the addresses coming from the execution unit; at least one function of correlation of these addresses; and at least one output of a bit for validating the fulfilling of conditions set by the correlation function.

    摘要翻译： 一种用于控制对由程序执行单元可访问的存储器的至少一个区域的访问的电路，包括第一指令地址输入; 至少一个第二数据地址输入，来自执行单元的地址; 至少一个这些地址相关的功能; 以及用于验证由相关函数设置的条件的满足的位的至少一个输出。

    Procedure for processing a virtual address for programming a DMA controller and associated system on a chip
    7.
    发明授权
    Procedure for processing a virtual address for programming a DMA controller and associated system on a chip 有权
    处理芯片上DMA控制器和相关系统的虚拟地址的程序

    公开(公告)号：US07337300B2

    公开(公告)日：2008-02-26

    申请号：US11154281

    申请日：2005-06-16

    申请人： Daniele Fronte ,  Jean Nicolai ,  Albert Martinez

    发明人： Daniele Fronte ,  Jean Nicolai ,  Albert Martinez

    IPC分类号： G06F9/34 ,  G06F9/26 ,  G06F12/00

    CPC分类号： G06F13/28

    摘要： A method is provided for processing a virtual address for a program requesting a DMA transfer. The program is designed to be run in user mode on a system on a chip that includes a central processing unit, a memory management unit, and a DMA controller. The virtual address is a source virtual address or a destination virtual address and has a size of N bits. According to the method, the virtual address is divided into at least two fields of bits. For each of the fields, there is created an N-bit address word comprising a prefix having a given value associated with the field and having more than 1 bit, and the field. The DMA controller is programmed using multiple store instructions that include one store instruction relating to each of the address words created.

    摘要翻译： 提供了一种用于处理请求DMA传输的程序的虚拟地址的方法。 该程序被设计为在包括中央处理单元，存储器管理单元和DMA控制器的芯片上的系统上以用户模式运行。 虚拟地址是源虚拟地址或目标虚拟地址，并且具有N位的大小。 根据该方法，虚拟地址被分成至少两个比特字段。 对于每个字段，创建了包括具有与该字段相关联并具有多于1位的给定值的前缀的N位地址字和该字段。 使用多个存储指令对DMA控制器进行编程，其中包括与创建的每个地址字相关的一个存储指令。

    Procedure for programming a DMA controller in a system on a chip and associated system on a chip
    8.
    发明申请
    Procedure for programming a DMA controller in a system on a chip and associated system on a chip 有权
    在芯片上的系统和芯片上的相关系统上对DMA控制器进行编程的过程

    公开(公告)号：US20060026311A1

    公开(公告)日：2006-02-02

    申请号：US11185529

    申请日：2005-07-20

    申请人： Jean Nicolai ,  Albert Martinez

    发明人： Jean Nicolai ,  Albert Martinez

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28 ,  G06F12/1081 ,  G06F2213/0038

    摘要： A procedure is provided for programming a DMA controller of a system on a chip that includes a CPU, an MMU, a DMA controller including source, destination, and size registers, and entities that are each identified by a physical address and addressable by applying that physical address to the address bus. In response to a first dedicated instruction of a user program, the virtual address is translated into a corresponding physical address, the corresponding physical address is applied to the address bus, a signal having a first value is delivered to the DMA controller, and a signal having a second value is delivered to the entities. When the signal delivered to the DMA controller has the first value, the source register or the destination register of the DMA controller is selected and the corresponding physical address on the address bus is stored in the selected register.

    摘要翻译： 提供了一种用于对包括CPU，MMU，包括源，目的地和大小寄存器的DMA控制器的芯片上的系统的DMA控制器进行编程的程序，以及每个由物理地址标识并可通过应用该物理地址来寻址的实体 物理地址到地址总线。 响应于用户程序的第一专用指令，将虚拟地址转换为对应的物理地址，将对应的物理地址应用于地址总线，具有第一值的信号被传送到DMA控制器，并且信号 具有第二个值被传递给实体。 当传送到DMA控制器的信号具有第一个值时，选择DMA控制器的源寄存器或目标寄存器，并将地址总线上相应的物理地址存储在所选寄存器中。

    Method for ciphering a compressed audio or video stream preserving the coding syntax
    9.
    发明申请
    Method for ciphering a compressed audio or video stream preserving the coding syntax 审中-公开
    用于加密保留编码语法的压缩音频或视频流的方法

    公开(公告)号：US20050013438A1

    公开(公告)日：2005-01-20

    申请号：US10892889

    申请日：2004-07-15

    申请人： Jean Nicolai

    发明人： Jean Nicolai

    IPC分类号： H04N7/167 ,  H04L9/00

    CPC分类号： H04N19/61 ,  H04N7/1675 ,  H04N21/2347

    摘要： A method ciphers a standardized stream of data coded by a table of codewords of different lengths, wherein at least one part of the bits is ciphered which are such that, after randomly changing their value(s) and after replacing bit by bit in the codeword to be ciphered the non-ciphered bits with the ciphered bits, a codeword of the table of codewords is obtained.

    摘要翻译： 方法加密由不同长度的码字表编码的标准数据流，其中至少一部分比特被加密，这些比特在随机改变它们的值之后并且在代码字中逐位替换之后 为了用加密位来加密非加密比特，获得码字表的码字。

    High precision relative digital voltage measurement
    10.
    发明授权
    High precision relative digital voltage measurement 失效
    高精度相对数字电压测量

    公开(公告)号：US5798933A

    公开(公告)日：1998-08-25

    申请号：US667192

    申请日：1996-06-20

    申请人： Jean Nicolai

    发明人： Jean Nicolai

    IPC分类号： G01R19/25 ,  G01R19/165 ,  G01R19/252 ,  H02J7/00 ,  G05F1/08

    CPC分类号： H02J7/0081 ,  G01R19/16528

    摘要： This device determines a quantity corresponding to a linear function of a voltage to be detected, and includes a circuit for charging with a determined time constant a capacitor, and a microcontroller. The microcontroller compares the voltage across the capacitor to a predetermined threshold and then resets the voltage across the capacitor. A counter counts the time duration between the end of a capacitor reset and the time when it reaches the predetermined threshold and calculates the inverse of said duration. This data can then be used to signal the end of a process, such as the proper charging of rechargeable batteries.

    摘要翻译： 该装置确定对应于要检测的电压的线性函数的量，并且包括用于以电容器确定的时间常数进行充电的电路和微控制器。 微控制器将电容器两端的电压与预定的阈值进行比较，然后复位电容器两端的电压。 计数器计数电容器复位结束与达到预定阈值的时间之间的持续时间，并计算所述持续时间的倒数。 然后可以使用该数据来通知过程的结束，例如对可再充电电池的适当充电。