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公开(公告)号：US08148239B2
公开(公告)日：2012-04-03
申请号：US12646459
申请日：2009-12-23
CPC分类号： H01L21/6836 , G03F7/70433 , H01L23/544 , H01L2221/68327 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： Techniques are provided for efficient wafer layout, which include the use of an offset grid to optimize use of available wafer space. As such, the number of identical die that can be fabricated on the wafer can be increased, relative to a standard perpendicular grid. By adding additional registration marks, an increase in flexibility of where each row/column of fields can be printed is enabled. This increased level of freedom in-turn allows for the optimization of the number of die that each row/column can contain, and translates directly into an increase in the number of yielding die per wafer. In addition, techniques are provided that allow for the dicing of individual die in a non-Cartesian coordinated manner. However, conventional singulation techniques can be used as well, given attention to the offset grid lines.
摘要翻译： 提供了有效的晶片布局的技术，其包括使用偏移栅格来优化可用晶片空间的使用。 因此，相对于标准垂直网格，可以增加可在晶片上制造的相同模具的数量。 通过添加附加的注册标记，可以增加打印每行/列字段的灵活性。 这种增加的自由度反过来允许优化每个行/列可以包含的管芯的数量，并且直接转化为每个晶片的屈服管芯数量的增加。 此外，提供允许以非笛卡尔坐标方式切割各个模具的技术。 然而，也可以使用常规的分割技术，注意偏移网格线。
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公开(公告)号：US20110147897A1
公开(公告)日：2011-06-23
申请号：US12646459
申请日：2009-12-23
IPC分类号： H01L23/544 , H01L21/78
CPC分类号： H01L21/6836 , G03F7/70433 , H01L23/544 , H01L2221/68327 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： Techniques are provided for efficient wafer layout, which include the use of an offset grid to optimize use of available wafer space. As such, the number of identical die that can be fabricated on the wafer can be increased, relative to a standard perpendicular grid. By adding additional registration marks, an increase in flexibility of where each row/column of fields can be printed is enabled. This increased level of freedom in-turn allows for the optimization of the number of die that each row/column can contain, and translates directly into an increase in the number of yielding die per wafer. In addition, techniques are provided that allow for the dicing of individual die in a non-Cartesian coordinated manner. However, conventional singulation techniques can be used as well, given attention to the offset grid lines.
摘要翻译： 提供了有效的晶片布局的技术，其包括使用偏移栅格来优化可用晶片空间的使用。 因此，相对于标准垂直网格，可以增加可在晶片上制造的相同模具的数量。 通过添加附加的注册标记，可以增加打印每行/列字段的灵活性。 这种增加的自由度反过来允许优化每行/列可以包含的管芯的数量，并且直接转化为每个晶片的屈服模数的增加。 此外，提供允许以非笛卡尔坐标方式切割各个模具的技术。 然而，也可以使用常规的分割技术，注意偏移网格线。
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公开(公告)号：US20120162622A1
公开(公告)日：2012-06-28
申请号：US12977918
申请日：2010-12-23
CPC分类号： G03F1/38 , G03B27/42 , G03F7/70433
摘要： Techniques are provided for efficient lithography processing and wafer layout. In particular, the techniques can be used to reduce the number of sacrificial exposures along the wafer perimeter region. In one example embodiment, an exposure system reticle is configured with both a normal area (die yielding area) and a dumification area (non-yielding area at wafer perimeter), thereby allowing for lithographic processing in the non-yielding areas sufficient to facilitate successful processing in the adjacent die yielding areas, but without requiring additional sacrificial exposures. This reduction in sacrificial exposures translates to a significant improvement in fab capacity. The techniques can be implemented, for example, on any number of lithography tools having an adjustable reticle or reticle blind capability and in the context of any technology nodes, such as 95 nm and smaller. The lithography tool may produce wafers at a faster rate.
摘要翻译： 提供了有效的光刻处理和晶片布局的技术。 特别地，可以使用这些技术来减少沿着晶片周边区域的牺牲暴露的数量。 在一个示例性实施例中，曝光系统掩模版被配置为具有正常区域（模具屈服区域）和倾倒区域（晶圆周边的非屈服区域），从而允许在非产生区域中的平版印刷处理足以促成成功 在相邻模具产生区域中进行加工，但不需要额外的牺牲暴露。 牺牲暴露的这种减少意味着工厂容量的显着提高。 这些技术可以例如在具有可调节掩模版或掩模版盲能力的任何数量的光刻工具上并且在诸如95nm或更小的任何技术节点的上下文中实现。 光刻工具可以以更快的速率生产晶片。
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