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公开(公告)号：US20120162622A1
公开(公告)日：2012-06-28
申请号：US12977918
申请日：2010-12-23
CPC分类号： G03F1/38 , G03B27/42 , G03F7/70433
摘要： Techniques are provided for efficient lithography processing and wafer layout. In particular, the techniques can be used to reduce the number of sacrificial exposures along the wafer perimeter region. In one example embodiment, an exposure system reticle is configured with both a normal area (die yielding area) and a dumification area (non-yielding area at wafer perimeter), thereby allowing for lithographic processing in the non-yielding areas sufficient to facilitate successful processing in the adjacent die yielding areas, but without requiring additional sacrificial exposures. This reduction in sacrificial exposures translates to a significant improvement in fab capacity. The techniques can be implemented, for example, on any number of lithography tools having an adjustable reticle or reticle blind capability and in the context of any technology nodes, such as 95 nm and smaller. The lithography tool may produce wafers at a faster rate.
摘要翻译： 提供了有效的光刻处理和晶片布局的技术。 特别地，可以使用这些技术来减少沿着晶片周边区域的牺牲暴露的数量。 在一个示例性实施例中，曝光系统掩模版被配置为具有正常区域（模具屈服区域）和倾倒区域（晶圆周边的非屈服区域），从而允许在非产生区域中的平版印刷处理足以促成成功 在相邻模具产生区域中进行加工，但不需要额外的牺牲暴露。 牺牲暴露的这种减少意味着工厂容量的显着提高。 这些技术可以例如在具有可调节掩模版或掩模版盲能力的任何数量的光刻工具上并且在诸如95nm或更小的任何技术节点的上下文中实现。 光刻工具可以以更快的速率生产晶片。
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2.发明授权Sacrificial erosion control features for chemical-mechanical polishing process 失效用于化学机械抛光工艺的牺牲侵蚀控制功能
公开(公告)号：US6087733A
公开(公告)日：2000-07-11
申请号：US94541
申请日：1998-06-12
IPC分类号： H01L21/321 , H01L21/768 , H01L23/544 , H01L21/301 , H01L21/302 , H01L21/76
CPC分类号： H01L23/544 , H01L21/3212 , H01L21/7684 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002
摘要： A method and apparatus for compensating for the effects of nonuniform planarization in chemical-mechanical polishing (CMP) such as the erosion occurring from the removal of titanium nitride/tungsten films is disclosed. In the context of alignment marks, dummy marks are disposed on both sides of the actual alignment marks providing a similar feature density as the alignment marks. During the CMP, the dummy marks reside in the area of nonuniform erosion, leaving the actual marks in an area of uniform erosion. The present invention may also be used to control underlayer erosion variations in the high feature density device areas adjacent to the low feature density open areas by providing dummy features in the low feature density areas.
摘要翻译： 公开了一种用于补偿化学机械抛光（CMP）中不均匀平面化的影响的方法和装置，例如从去除氮化钛/钨膜而发生的侵蚀。 在对准标记的上下文中，虚拟标记设置在实际对准标记的两侧，提供与对准标记相似的特征密度。 在CMP期间，虚拟标记位于不均匀侵蚀的区域，留下实际痕迹在均匀侵蚀的区域。 本发明还可以用于通过在低特征密度区域中提供虚拟特征来控制与低特征密度开放区域相邻的高特征密度装置区域中的底层侵蚀变化。
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3.发明授权Design structures of and simplified methods for forming field emission microtip electron emitters 失效用于形成场发射微带电子发射体的设计结构和简化方法公开(公告)号：US06771011B2
公开(公告)日：2004-08-03
申请号：US10383966
申请日：2003-03-07
IPC分类号： H01J1304
CPC分类号： H01J9/025
摘要： Electron emission structures formed using standard semiconductor processes on a substrate first prepared with a topographical feature are disclosed. At least one layer of a first material is concurrently deposited on the substrate and etched from the substrate to form an atomically sharp feature. An at least one layer of a second material is deposited over the atomically sharp feature. A conductive layer is deposited over the at least one layer of the second material. A selected area of material is removed from the conductive layer and the at least one layer of second material to expose the atomically sharp feature. Finally, electrical connectivity is provided to elements of the electron emission structure.
摘要翻译： 公开了首先使用形貌特征制备的基板上使用标准半导体工艺形成的电子发射结构。 至少一层第一材料同时沉积在衬底上并从衬底上蚀刻以形成原子锋利的特征。 在原子锋利特征上沉积至少一层第二材料。 导电层沉积在第二材料的至少一层上。 从导电层和至少一层第二材料中去除选择的材料区域以暴露原子锋利的特征。 最后，电连接被提供给电子发射结构的元件。
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公开(公告)号：US06572425B2
公开(公告)日：2003-06-03
申请号：US09820338
申请日：2001-03-28
IPC分类号： H01J902
CPC分类号： H01J9/025
摘要： Electron emission structures formed using standard semiconductor processes on a substrate first prepared with a topographical feature are disclosed. At least one layer of a first material is concurrently deposited on the substrate and etched from the substrate to form an atomically sharp feature. An at least one layer of a second material is deposited over the atomically sharp feature. A conductive layer is deposited over the at least one layer of the second material. A selected area of material is removed from the conductive layer and the at least one layer of second material to expose the atomically sharp feature. Finally, electrical connectivity is provided to elements of the electron emission structure.
摘要翻译： 公开了首先使用形貌特征制备的基板上使用标准半导体工艺形成的电子发射结构。 至少一层第一材料同时沉积在衬底上并从衬底上蚀刻以形成原子锋利的特征。 在原子锋利特征上沉积至少一层第二材料。 导电层沉积在第二材料的至少一层上。 从导电层和至少一层第二材料中去除选择的材料区域以暴露原子锋利的特征。 最后，电连接被提供给电子发射结构的元件。
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