公开(公告)号：USRE43573E1

公开(公告)日：2012-08-14

申请号：US13168832

申请日：2011-06-24

Applicant: Alexander J. Eglit

Inventor： Alexander J. Eglit

IPC: G09G5/00

CPC classification number: H03L7/093 ,  G09G5/008 ,  H03L7/07 ,  H03L7/085

Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal. This invention is directed to a method of scaling a source image formed of a number of source image elements to provide a destination image formed of a number of destination image elements using a line buffer and no frame buffer.

Abstract translation: 一种用于恢复与模拟显示数据相关联的时间参考信号的数字显示单元中的时钟恢复电路。 时钟恢复电路包括在数字域中实现的锁相环（PLL）和模拟滤波器，以消除来自PLL的输出信号的任何不期望的频率。 PLL包括独立的控制回路，分别跟踪时间参考信号的长期频率漂移和瞬态相位差。 通过提供这种独立的控制回路，所产生的时钟可以与时间参考信号更好地同步。 本发明涉及一种缩放由多个源图像元素形成的源图像的方法，以使用线缓冲器并且不使用帧缓冲器来提供由多个目的地图像元素形成的目的地图像。

公开(公告)号：USRE40859E1

公开(公告)日：2009-07-21

申请号：US10720001

申请日：2003-11-20

Applicant: Alexander J. Eglit

Inventor： Alexander J. Eglit

IPC: G09G5/00 ,  G06F15/00 ,  H04N9/475 ,  H03L7/00

CPC classification number: H03L7/093 ,  G09G5/008 ,  H03L7/07 ,  H03L7/085

Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal. A system and method for displaying an analog source image by a digital display unit. A converter circuit generates a plurality of digital source image elements from an analog source image based upon a sampling clock signal synchronized with a time reference signal associated with the analog source image. A scaler unit receives the digital source image elements in accordance with a first clock signal, scales the source image elements independently in both vertical and horizontal directions to form destination image elements, and provides the destination image elements to the display unit in accordance with a second clock signal. The first clock signal and the second clock signal are arranged such that a source frame rate and a destination frame rate are substantially equal.

Abstract translation: <？delete-start id =“DEL-S-00001”date =“20090721”？>数字显示单元中的时钟恢复电路，用于恢复与模拟显示数据相关联的时间参考信号。 时钟恢复电路包括在数字域中实现的锁相环（PLL）和模拟滤波器，以消除来自PLL的输出信号的任何不期望的频率。 PLL包括独立的控制回路，以分别跟踪时间参考信号的长期频率漂移和瞬态相位差。 通过提供这种独立的控制回路，所产生的时钟可以更好地与时间参考信号同步。<？delete-end id =“DEL-S-00001”？> <？insert-start id =“INS-S-00001” date =“20090721”？>用于通过数字显示单元显示模拟源图像的系统和方法。 A转换器电路基于与与模拟源图像相关联的时间参考信号同步的采样时钟信号，从模拟源图像生成多个数字源图像元素。 缩放器单元根据第一时钟信号接收数字源图像元素，在垂直和水平方向上独立地缩放源图像元素以形成目的地图像元素，并且根据第二时间向目标图像元素提供目标图像元素 时钟信号。 第一时钟信号和第二时钟信号被布置为使得源帧速率和目的地帧速率基本相等。<？insert-end id =“INS-S-00001”？>

公开(公告)号：US06320574B1

公开(公告)日：2001-11-20

申请号：US09082070

申请日：1998-05-20

Applicant: Alexander J. Eglit

Inventor： Alexander J. Eglit

IPC: G09G512

CPC classification number: H03L7/093 ,  G09G5/008 ,  H03L7/07 ,  H03L7/085

Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal.

Abstract translation: 一种用于恢复与模拟显示数据相关联的时间参考信号的数字显示单元中的时钟恢复电路。 时钟恢复电路包括在数字域中实现的锁相环（PLL）和模拟滤波器，以消除来自PLL的输出信号的任何不期望的频率。 PLL包括独立的控制回路，以分别跟踪时间参考信号的长期频率漂移和瞬态相位差。 通过提供这种独立的控制回路，所产生的时钟可以与时间参考信号更好地同步。

公开(公告)号：USRE41192E1

公开(公告)日：2010-04-06

申请号：US11408669

申请日：2006-04-21

Applicant: Alexander J. Eglit

Inventor： Alexander J. Eglit

IPC: G09G5/00

CPC classification number: H03L7/093 ,  G09G5/008 ,  H03L7/07 ,  H03L7/085

Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal. Scaling a source image formed of a number of source image elements to provide a destination image formed of a number of destination image elements using a line buffer and no frame buffer.

Abstract translation: 一种用于恢复与模拟显示数据相关联的时间参考信号的数字显示单元中的时钟恢复电路。 时钟恢复电路包括在数字域中实现的锁相环（PLL）和模拟滤波器，以消除来自PLL的输出信号的任何不期望的频率。 PLL包括独立的控制回路，以分别跟踪时间参考信号的长期频率漂移和瞬态相位差。 通过提供这种独立的控制回路，所产生的时钟可以与时间参考信号更好地同步。 缩放由多个源图像元素形成的源图像，以使用线缓冲器并且不使用帧缓冲器来提供由多个目的地图像元素形成的目的地图像。

公开(公告)号：US07209133B2

公开(公告)日：2007-04-24

申请号：US10359734

申请日：2003-02-07

Applicant: Alexander J. Eglit ,  Sridhar Kotha ,  Vlad Bril

Inventor： Alexander J. Eglit ,  Sridhar Kotha ,  Vlad Bril

IPC: G09G5/00 ,  G09G3/18

CPC classification number: G09G5/005 ,  G09G5/006 ,  G09G5/008

Abstract: A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform (DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.

Abstract translation: 计算机系统中的显示控制器控制具有至少一个固定分辨率平板显示器的计算机系统中的图形显示数据的异步输出。 固定面板显示器可能会出现显示非本机分辨率的问题，特别是在较低分辨率下。 本发明的控制器使用时基转换器，水平和垂直离散时间振荡器（DTO）和多相内插器，其可以是基于离散余弦变换（DCT）的方式，以将图形显示数据从原始分辨率异步地扩展到至少一个 分辨率适合在固定分辨率面板上显示。 图形数据也可以异步地输出到CRT。 时基转换器接收频率相关的输入参数，并以期望的输出分辨率产生至少一个异步输出。

公开(公告)号：US6002446A

公开(公告)日：1999-12-14

申请号：US971825

申请日：1997-11-17

Applicant: Alexander J. Eglit

Inventor： Alexander J. Eglit

IPC: H04N5/228 ,  G06T3/40 ,  G09G3/20 ,  H04N5/262 ,  H04N7/01

CPC classification number: G09G5/006 ,  G06T3/4007 ,  G09G5/00 ,  G09G5/18 ,  H04N7/0105 ,  G09G2340/0414 ,  G09G2340/0421 ,  G09G2340/0442 ,  G09G2360/02 ,  G09G3/2096

Abstract: An upscaler for upscaling a source image to generate a destination image without requiring large buffers. The aspect ratio (ratio of the length of the source image to that of the width) of the source image need not equal the aspect ratio of the destination image. The source image pixel data is received at a first clock rate and the destination image is generated at a second clock rate. The second clock rate is computed such that the frame rate at which the source image is received is the same as the frame rate at which the upscaled image is generated. Because of such a clock rate, the upscaler may be implemented using only a line buffer.

Abstract translation: 用于升级源图像以生成目标图像而不需要大的缓冲区的分频器。 源图像的宽高比（源图像的长度与宽度的长度的比率）不需要等于目的图像的宽高比。 以第一时钟速率接收源图像像素数据，并以第二时钟速率生成目标图像。 计算第二时钟速率，使得接收源图像的帧速率与生成放大的图像的帧速率相同。 由于这样的时钟速率，可以仅使用行缓冲器来实现升档器。

公开(公告)号：USRE42615E1

公开(公告)日：2011-08-16

申请号：US12624053

申请日：2009-11-23

Applicant: Alexander J. Eglit

Inventor： Alexander J. Eglit

IPC: G09G5/00

CPC classification number: H03L7/093 ,  G09G5/008 ,  H03L7/07 ,  H03L7/085

Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal. Scaling a source image formed of a number of source image elements to provide a destination image formed of a number of destination image elements using a line buffer and no frame buffer.

Abstract translation: 一种用于恢复与模拟显示数据相关联的时间参考信号的数字显示单元中的时钟恢复电路。 时钟恢复电路包括在数字域中实现的锁相环（PLL）和模拟滤波器，以消除来自PLL的输出信号的任何不期望的频率。 PLL包括独立的控制回路，以分别跟踪时间参考信号的长期频率漂移和瞬态相位差。 通过提供这种独立的控制回路，所产生的时钟可以与时间参考信号更好地同步。 缩放由多个源图像元素形成的源图像，以使用线缓冲器并且不使用帧缓冲器来提供由多个目的地图像元素形成的目的地图像。

公开(公告)号：US6067071A

公开(公告)日：2000-05-23

申请号：US673793

申请日：1996-06-27

Applicant: Sridhar Kotha ,  Vlad Bril ,  Alexander J. Eglit ,  Robin Sungsoo Han

Inventor： Sridhar Kotha ,  Vlad Bril ,  Alexander J. Eglit ,  Robin Sungsoo Han

IPC: G02F1/133 ,  G06F17/50 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00 ,  G09G5/18

CPC classification number: G09G5/005 ,  G09G2340/0407 ,  G09G5/006 ,  G09G5/18

Abstract: A display controller in a computer system controls the output of graphics display data in a computer system having a fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a Discrete Time Oscillator (DTO) based clock divider and DCT based polyphase interpolation to upscale graphics display data from a first resolution to the panel resolution. DTO clock divider circuit synchronizes scan clocks between the input resolution and the desired output resolution. Within graphics display area, MVA.TM. display at greater color depth and resolution may be accommodated by additional DTO divider and interpolation steps.

Abstract translation: 计算机系统中的显示控制器控制具有固定分辨率平板显示器的计算机系统中的图形显示数据的输出。 固定面板显示器可能会显示非本地分辨率，特别是在较低分辨率下。 本发明的控制器使用基于离散时间振荡器（DTO）的时钟分频器和基于DCT的多相插值来将图形显示数据从第一分辨率升高到面板分辨率。 DTO时钟分频器电路在输入分辨率和所需输出分辨率之间同步扫描时钟。 在图形显示区域内，可以通过附加的DTO分频器和插值步骤来适应更大颜色深度和分辨率的MVA TM显示。

公开(公告)号：US5896179A

公开(公告)日：1999-04-20

申请号：US414996

申请日：1995-03-31

Applicant: Alexander J. Eglit

Inventor： Alexander J. Eglit

IPC: H04N9/78 ,  G09G1/28 ,  G09G5/00 ,  G09G5/18 ,  H04N5/44 ,  H04N9/64 ,  H04N11/14

CPC classification number: H04N5/44 ,  G09G1/285 ,  H04N21/4113 ,  H04N9/641

Abstract: In a graphics card of a computer, a circuit is provided for displaying graphic presentations generated by the card on an external TV set. A TV adapter controls a horizontal state machine of a CRT controller so as to delay generation of CRT timing signals by a time period variable with horizontal lines. As a result, a composite video signal is provided with a time-base variable front porch to simulate VTR video signals. In response to the generated composite video signal, the TV set switches into a VTR mode to disable a comb filter used for separating luminance and chrominance components of a broadcast television signal.

Abstract translation: 在计算机的图形卡中，提供用于显示由外部电视机上的卡生成的图形呈现的电路。 电视适配器控制CRT控制器的水平状态机，以便延迟CRT定时信号的产生与水平线变化的时间段。 结果，复合视频信号具有时基可变前沿以模拟VTR视频信号。 响应于所生成的复合视频信号，电视机切换到VTR模式以禁用用于分离广播电视信号的亮度和色度分量的梳状滤波器。

公开(公告)号：US5712688A

公开(公告)日：1998-01-27

申请号：US764875

申请日：1996-12-03

Applicant: Alexander J. Eglit

Inventor： Alexander J. Eglit

IPC: H04N9/78 ,  G09G1/28 ,  G09G5/00 ,  G09G5/18 ,  H04N5/44 ,  H04N9/64 ,  H04N9/475

CPC classification number: H04N5/44 ,  G09G1/285 ,  H04N21/4113 ,  H04N9/641

Abstract: In a graphics card of a computer, a circuit is provided for displaying graphic presentations generated by the card on an external TV set. A TV adapter controls a horizontal state machine of a CRT controller so as to delay generation of CRT timing signals by a time period variable with horizontal lines. As a result, a composite video signal is provided with a time-base variable front porch to simulate VTR video signals. In response to the generated composite video signal, the TV set switches into a VTR mode to disable a comb filter used for separating luminance and chrominance components of a broadcast television signal.

Abstract translation: 在计算机的图形卡中，提供用于显示由外部电视机上的卡生成的图形呈现的电路。 电视适配器控制CRT控制器的水平状态机，以便延迟CRT定时信号的产生与水平线变化的时间段。 结果，复合视频信号具有时基可变前沿以模拟VTR视频信号。 响应于所生成的复合视频信号，电视机切换到VTR模式以禁用用于分离广播电视信号的亮度和色度分量的梳状滤波器。