公开(公告)号：US20230244626A1

公开(公告)日：2023-08-03

申请号：US17824824

申请日：2022-05-25

申请人： Alibaba (China) Co., Ltd.

发明人： Liang HAN ,  ChengYuan WU ,  Guoyu ZHU ,  Yang JIAO ,  Rong ZHONG ,  Yunxiao ZOU

IPC分类号： G06F13/40

CPC分类号： G06F13/4068

摘要： The presented systems enable efficient and effective network communications. In one embodiment, a system comprises a parallel processing unit (PPU) included in a chip and a plurality of interconnects in an inter-chip network (ICN) configured to communicatively couple a plurality of PPUs that communicate with one another via the ICN. Corresponding communications are configured in accordance with routing tables. The routing tables can be stored and reside in registers of an ICN subsystem included in the PPU and include indications of minimum links available to forward a communication from the PPU and another PPU. Respective ones of the routing tables include indications of a correlation between the minimum links and respective ones of a plurality of egress ports that are available for communication coupling to the respective ones of PPUs that are possible destination PPUs. The routing tables can include indications of a single path between two PPUs per respective information communication flow.

公开(公告)号：US20230176737A1

公开(公告)日：2023-06-08

申请号：US17824804

申请日：2022-05-25

申请人： Alibaba (China) Co., Ltd.

发明人： Liang HAN ,  Yunxiao ZOU

IPC分类号： G06F3/06

CPC分类号： G06F3/0611 ,  G06F3/0644 ,  G06F3/0673

摘要： The time required to read from and write to multi-terabyte memory chips in an inter-chip network can be reduced by breaking each memory chip into a number of memory spaces, and then individually addressing each memory space with an address that identifies the memory space, a line number within the memory space, and a number of transmit/receive ports to be used to access the line number.

公开(公告)号：US20230185749A1

公开(公告)日：2023-06-15

申请号：US17824814

申请日：2022-05-25

申请人： Alibaba (China) Co., Ltd.

发明人： Liang HAN ,  ChengYuan WU ,  Guoyu ZHU ,  Rong ZHONG ,  Yang JIAO ,  Ye LU ,  Wei WU ,  Yunxiao ZOU ,  Li YIN

IPC分类号： G06F13/40

CPC分类号： G06F13/4022 ,  G06F13/4063 ,  G06F2213/0026

摘要： A system includes a high-bandwidth inter-chip network (ICN) that allows communication between neural network processing units (NPUs) in the system. For example, the ICN allows an NPU to communicate with other NPUs on the same compute node (server) and also with NPUs on other compute nodes (servers). Communication can be at the direct memory access (DMA) command level and at the finer-grained load/store instruction level. The ICN system and the programming model allows NPUs in the system to communicate without using a traditional network (e.g., Ethernet) that uses a relatively narrow and slow Peripheral Component Interconnect Express (PCIe) bus.