公开(公告)号：US20240405124A1

公开(公告)日：2024-12-05

申请号：US18327200

申请日：2023-06-01

Applicant: Allegro MicroSystems, LLC

Inventor： Yu-Chun Li ,  Thomas S. Chung ,  Maxim Klebanov ,  Chung C. Kuo ,  James M. McClay ,  Robert A. Wilson

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

Abstract: According to one aspect of the present disclosure, a semiconductor device includes a substrate having a first type dopant. In some embodiments, the semiconductor device also includes an epitaxial layer above the substrate, having a second type dopant and a top region. In some embodiments, the semiconductor device also includes a trench in the top region of the epitaxial layer; at least one doped ring implanted in the epitaxial layer below the trench; and a dielectric material filling within the trench. In some embodiments, there is a twelve-sided body tie in the epitaxial layer, wherein the sides of the twelve-sided body tie are not all equal to each other.