公开(公告)号：US20250140681A1

公开(公告)日：2025-05-01

申请号：US18499345

申请日：2023-11-01

Applicant: Allegro MicroSystems, LLC

Inventor： Felix Palumbo ,  Thomas S. Chung ,  Maxim Klebanov

IPC: H01L23/522

Abstract: Example embodiments include methods and apparatus for a structure having a capacitor, where the structure includes a plurality of inter-metal dielectric (IMD) layers above a substrate, a plurality of metal layers between respective IMD layers. In embodiments, BEOL metal regions and interconnects form plates of the capacitor. In example embodiments, lateral capacitors can be formed away from the substrate.

公开(公告)号：US20240063310A1

公开(公告)日：2024-02-22

申请号：US17819957

申请日：2022-08-16

Applicant: Allegro MicroSystems, LLC

Inventor： Yu-Chun Li ,  Felix Palumbo ,  Chung C. Kuo ,  Thomas S. Chung ,  Maxim Klebanov

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/872 ,  H01L29/0623 ,  H01L29/402

Abstract: A Schottky diode includes a substrate having a first type dopant, a buried layer within the substrate and having a second type dopant, an epitaxial layer above the buried layer and having the second type dopant, a plurality of rings within the epitaxial layer and having the first type dopant, wherein the plurality of rings comprises an L-shaped ring, a shallow trench isolation (STI) layer at the top region of the epitaxial layer, an anode, a cathode spaced from the anode by the STI layer, and wherein the buried layer has an open region substantially vertically aligned with the anode.

公开(公告)号：US12119413B2

公开(公告)日：2024-10-15

申请号：US17819957

申请日：2022-08-16

Applicant: Allegro MicroSystems, LLC

Inventor： Yu-Chun Li ,  Felix Palumbo ,  Chung C. Kuo ,  Thomas S. Chung ,  Maxim Klebanov

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/872 ,  H01L29/0623 ,  H01L29/402

Abstract: A Schottky diode includes a substrate having a first type dopant, a buried layer within the substrate and having a second type dopant, an epitaxial layer above the buried layer and having the second type dopant, a plurality of rings within the epitaxial layer and having the first type dopant, wherein the plurality of rings comprises an L-shaped ring, a shallow trench isolation (STI) layer at the top region of the epitaxial layer, an anode, a cathode spaced from the anode by the STI layer, and wherein the buried layer has an open region substantially vertically aligned with the anode.

公开(公告)号：US20240405124A1

公开(公告)日：2024-12-05

申请号：US18327200

申请日：2023-06-01

Applicant: Allegro MicroSystems, LLC

Inventor： Yu-Chun Li ,  Thomas S. Chung ,  Maxim Klebanov ,  Chung C. Kuo ,  James M. McClay ,  Robert A. Wilson

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

Abstract: According to one aspect of the present disclosure, a semiconductor device includes a substrate having a first type dopant. In some embodiments, the semiconductor device also includes an epitaxial layer above the substrate, having a second type dopant and a top region. In some embodiments, the semiconductor device also includes a trench in the top region of the epitaxial layer; at least one doped ring implanted in the epitaxial layer below the trench; and a dielectric material filling within the trench. In some embodiments, there is a twelve-sided body tie in the epitaxial layer, wherein the sides of the twelve-sided body tie are not all equal to each other.

公开(公告)号：US20230253507A1

公开(公告)日：2023-08-10

申请号：US17650418

申请日：2022-02-09

Applicant: Allegro MicroSystems, LLC

Inventor： Thomas S. Chung ,  Maxim Klebanov ,  Sundar Chetlur ,  James McClay

IPC: H01L29/788 ,  H01L29/08 ,  H01L29/66 ,  G11C16/10 ,  G11C16/14

CPC classification number: H01L29/7883 ,  G11C16/10 ,  G11C16/14 ,  H01L29/0847 ,  H01L29/66825

Abstract: In one aspect, a flash memory cell includes a well having a first-type dopant, a source having a second-type dopant and formed within the well, a drain having the second-type dopant and formed within the well, a floating gate above the well, a control gate above the floating gate, an oxide compound disposed between the floating gate and the control gate, and a tunnel oxide disposed between the floating gate and the well. The flash memory cell is configured, in one of a program mode or an erase mode, to move an electron from the source to the floating gate. The flash memory cell is configured, in the other one of the program or the erase mode, to move an electron is from the floating gate to the drain.

公开(公告)号：US12249646B2

公开(公告)日：2025-03-11

申请号：US17695029

申请日：2022-03-15

Applicant: Allegro MicroSystems, LLC

Inventor： Thomas S. Chung ,  Chung C. Kuo ,  Maxim Klebanov ,  Sundar Chetlur

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08

Abstract: In one aspect, a double-diffused metal oxide semiconductor (DMOS) includes a region of a semiconductor having a first region of a semiconductor having a first-type dopant, a first well having a second-type dopant, a dielectric within the first well, the dielectric having a bottom surface and a top surface opposite the bottom surface, a gate disposed on the top surface of the dielectric. The gate, the dielectric and the first well are configured to form a first reduced surface field (RESURF). The bottom surface of the dielectric has a first portion and a second portion, and the first portion of the bottom surface of the dielectric is closer to the top surface of the dielectric than the second portion of the bottom surface of the dielectric.

公开(公告)号：US20240120371A1

公开(公告)日：2024-04-11

申请号：US18045528

申请日：2022-10-11

Applicant: Allegro MicroSystems, LLC

Inventor： James McClay ,  Maxim Klebanov ,  Sundar Chetlur ,  Thomas S. Chung

IPC: H01L29/06 ,  H01L27/11524 ,  H01L29/788

CPC classification number: H01L29/0646 ,  H01L27/11524 ,  H01L29/7883

Abstract: Methods and apparatus for a device that includes a circuit, such as a memory cell, and an isolation structure to electrically isolate the circuit cell. The isolation structure can include a p-type substrate, a first series of p-type material extending to the p-type substrate, and a second series of p-type material extending to the p-type substrate. The first series of p-type material, the p-type substrate, and the second series of p-type material surrounds a first side, a second side, and a bottom of the circuit cell to electrically isolate the circuit cell with continuous p-type material. In some embodiments, the first series of p-type material comprises p-type well regions. In some embodiments, the first series of p-type material comprises deep trench isolation.

公开(公告)号：US20230413687A1

公开(公告)日：2023-12-21

申请号：US17807196

申请日：2022-06-16

Applicant: Allegro MicroSystems, LLC

Inventor： Thomas S. Chung ,  Maxim Klebanov ,  Sundar Chetlur

IPC: H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  G01R33/07

CPC classification number: H01L43/04 ,  H01L43/065 ,  H01L43/10 ,  G01R33/077

Abstract: In one aspect, a Hall effect device includes an implantation layer; an epitaxial layer located above the implantation layer; a trench filled with a dielectric material and extending from a top surface of the epitaxial layer into the implantation layer and defining an enclosed region; a buried layer the epitaxial layer from the implantation layer within the enclosed region; and a contact pad located on the epitaxial layer. The trench reduces a current from the contact pad from traveling in a lateral direction orthogonal to a vertical direction and enables the current to travel in the vertical direction.

公开(公告)号：US20230299195A1

公开(公告)日：2023-09-21

申请号：US17695029

申请日：2022-03-15

Applicant: Allegro MicroSystems, LLC

Inventor： Thomas S. Chung ,  Chung C. Kuo ,  Maxim Klebanov ,  Sundar Chetlur

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0852

Abstract: In one aspect, a double-diffused metal oxide semiconductor (DMOS) includes a region of a semiconductor having a first region of a semiconductor having a first-type dopant, a first well having a second-type dopant, a dielectric within the first well, the dielectric having a bottom surface and a top surface opposite the bottom surface, a gate disposed on the top surface of the dielectric. The gate, the dielectric and the first well are configured to form a first reduced surface field (RESURF). The bottom surface of the dielectric has a first portion and a second portion, and the first portion of the bottom surface of the dielectric is closer to the top surface of the dielectric than the second portion of the bottom surface of the dielectric.