公开(公告)号：US10884092B2

公开(公告)日：2021-01-05

申请号：US16214768

申请日：2018-12-10

Applicant: Allegro MicroSystems, LLC

Inventor： Nicolas Rigoni ,  Octavio H. Alpago ,  Nicolas Rafael Biberidis ,  Hernán D. Romero

IPC: G01R35/00 ,  G01R33/02 ,  G01R33/00

Abstract: A magnetic field sensor includes a first magnetic field sensing element first generating a first signal having a first axis of maximum sensitivity, a second magnetic field sensing element for generating a second signal and having a second axis of maximum sensitivity, one or more detectors for receiving an output of the first magnetic field sensing element or the second magnetic field sensing element, and a processor that receives an output of the one or more detectors and uses the output of the one or more detectors to calculate a first constant Kc and a second constant Ks and then uses Kc and Ks to compensate for an orthogonality error between the first axis of maximum sensitivity and second axis of maximum sensitivity. The detectors include peak detectors and/or zero-crossing detectors that compare the output of the first input signal or the second input signal with a threshold or zero.

公开(公告)号：US20200020412A1

公开(公告)日：2020-01-16

申请号：US16033722

申请日：2018-07-12

Applicant: Allegro MicroSystems, LLC

Inventor： Nicolas Rafael Biberidis ,  Octavio H. Alpago ,  Nicolas Rigoni

IPC: G11C29/38 ,  G06F11/10 ,  G11C29/52 ,  G11C29/44 ,  G01R33/07 ,  G01R33/09

Abstract: A method for multi-level memory safety for a sensor integrated circuit can include loading a blocking bit into a volatile memory from a non-volatile memory and providing the blocking bit to a gating circuit from the volatile memory. Further, the method may include the gating circuit determining whether to provide a default value to a functional logic based upon the provided blocking bit.

公开(公告)号：US10706948B2

公开(公告)日：2020-07-07

申请号：US16033722

申请日：2018-07-12

Applicant: Allegro MicroSystems, LLC

Inventor： Nicolas Rafael Biberidis ,  Octavio H. Alpago ,  Nicolas Rigoni

IPC: G11C29/38 ,  G06F11/10 ,  G11C29/52 ,  G01R33/07 ,  G01R33/09 ,  G11C29/44 ,  G11C11/56

Abstract: A method for multi-level memory safety for a sensor integrated circuit can include loading a blocking bit into a volatile memory from a non-volatile memory and providing the blocking bit to a gating circuit from the volatile memory. Further, the method may include the gating circuit determining whether to provide a default value to a functional logic based upon the provided blocking bit.

公开(公告)号：US20190113592A1

公开(公告)日：2019-04-18

申请号：US16214768

申请日：2018-12-10

Applicant: Allegro MicroSystems, LLC

Inventor： Nicolas Rigoni ,  Octavio H. Alpago ,  Nicolas Rafael Biberidis ,  Hernán D. Romero

IPC: G01R35/00 ,  G01R33/02

Abstract: A magnetic field sensor includes a first magnetic field sensing element first generating a first signal having a first axis of maximum sensitivity, a second magnetic field sensing element for generating a second signal and having a second axis of maximum sensitivity, one or more detectors for receiving an output of the first magnetic field sensing element or the second magnetic field sensing element, and a processor that receives an output of the one or more detectors and uses the output of the one or more detectors to calculate a first constant Kc and a second constant Ks and then uses Kc and Ks to compensate for an orthogonality error between the first axis of maximum sensitivity and second axis of maximum sensitivity. The detectors include peak detectors and/or zero-crossing detectors that compare the output of the first input signal or the second input signal with a threshold or zero.