利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

7 条记录 (耗时 0.017 秒)

    Methods and apparatuses for time and space switching of SONET framed data
    2.
    发明授权
    Methods and apparatuses for time and space switching of SONET framed data 有权
    SONET框架数据的时间和空间切换方法和装置

    公开(公告)号：US07039072B1

    公开(公告)日：2006-05-02

    申请号：US09661498

    申请日：2000-09-14

    申请人： Alnoor M. Shivji ,  Sunil Tomar ,  Shashij Singh

    发明人： Alnoor M. Shivji ,  Sunil Tomar ,  Shashij Singh

    IPC分类号： H04J3/02 ,  H04L12/50

    CPC分类号： H04J3/1617 ,  H04J2203/0012 ,  H04J2203/0026 ,  H04J2203/0032 ,  H04J2203/0046 ,  H04J2203/0082

    摘要： Multiple streams of bits are received. One or more bits are selected from a stream of bits based, at least in part, on a space control register value and a time control register value. In one embodiment, a time control register stores a value indicating a selected bit from a sequence of bits, a counter counts bits in the sequence of bits from a predetermined bit, and a comparator is coupled to the time control register and to the counter to generate a load signal when a value stored in the time control register and a value provided by the counter are equal. The load signal causes the latch to load a value output by the multiplexer.

    摘要翻译： 接收多个比特流。 至少部分地基于空间控制寄存器值和时间控制寄存器值从位流中选择一个或多个位。 在一个实施例中，时间控制寄存器存储指示来自比特序列的所选位的值，计数器从预定比特计数比特序列中的比特，并且比较器耦合到时间控制寄存器和计数器 当存储在时间控制寄存器中的值和由计数器提供的值相等时，产生负载信号。 负载信号使锁存器加载由多路复用器输出的值。

    Layouts for an integrated circuit to perform time and space switching of SONET framed data
    4.
    发明授权
    Layouts for an integrated circuit to perform time and space switching of SONET framed data 有权
    用于集成电路的布局来执行SONET成帧数据的时间和空间切换

    公开(公告)号：US06834049B1

    公开(公告)日：2004-12-21

    申请号：US09661494

    申请日：2000-09-14

    申请人： Sunil Tomar ,  Shashij Singh

    发明人： Sunil Tomar ,  Shashij Singh

    IPC分类号： H04L1266

    CPC分类号： H04Q11/0478 ,  H04J2203/0007 ,  H04J2203/0008 ,  H04J2203/0025

    摘要： Methods and apparatuses for laying out an integrated circuit include a first plurality of I/O ports that are positioned along the first side, a plurality of queues that are coupled to the first plurality of I/O ports, a first bus that is positioned extending from the plurality of queues toward the second side to couple a control circuit to the plurality of queues, second plurality of I/O ports that are positioned along the third side and the fourth side, and a second bus that is positioned between the control circuit and the second plurality of I/O ports to couple the control circuit to the second plurality of I/O ports, wherein the first bus and the second bus are positioned such that the respective bus lines do not cross over each other. A time and space switching apparatus and component cell permit a bit within a data line to be selected.

    摘要翻译： 用于布置集成电路的方法和装置包括沿着第一侧定位的第一多个I / O端口，耦合到第一多个I / O端口的多个队列，第一总线，其被定位为延伸 从多个队列朝向第二侧，将控制电路耦合到多个队列，沿着第三侧和第四侧定位的第二多个I / O端口，以及位于控制电路之间的第二总线 以及第二多个I / O端口以将控制电路耦合到第二多个I / O端口，其中第一总线和第二总线被定位成使得相应的总线线路不互相交叉。 时间和空间交换设备和组件单元允许选择数据线内的位。

    Methods and apparatuses for serial transfer of SONET framed data between components of a SONET system
    5.
    发明授权
    Methods and apparatuses for serial transfer of SONET framed data between components of a SONET system 有权
    在SONET系统的组件之间串行传输SONET成帧数据的方法和装置

    公开(公告)号：US06944190B1

    公开(公告)日：2005-09-13

    申请号：US09660837

    申请日：2000-09-14

    申请人： Sunil Tomar ,  Arvind Bhaskar Patwardhan ,  Srinivasarao Neelamraju

    发明人： Sunil Tomar ,  Arvind Bhaskar Patwardhan ,  Srinivasarao Neelamraju

    IPC分类号： H04J3/06 ,  H04J3/16 ,  H04Q11/04 ,  H04J3/04

    CPC分类号： H04J3/1611 ,  H04J3/0688 ,  H04J2203/0007 ,  H04J2203/0008 ,  H04J2203/0025 ,  H04J2203/0026

    摘要： A plurality of transmission circuits transmit data over one or more output lines. A plurality of receiving circuits receive data over one or more of a set of input lines A plurality of parallel-serial conversion circuits coupled to the plurality of transmission circuits and to the plurality of receiving circuits, the plurality of conversion circuits to convert parallel signals to one or more sets of serial signals and to send the converted serial signals to one or more corresponding transmission circuits, and to receive one or more sets of serial signals from one or more of the receiving circuits and to convert the serial signals to parallel signals.

    摘要翻译： 多个发送电路通过一条或多条输出线路发送数据。 多个接收电路通过一组输入线路中的一个或多个接收数据，多个并行 - 串行转换电路耦合到多个发送电路和多个接收电路，多个转换电路将并行信号转换为 一组或多组串行信号，并将转换的串行信号发送到一个或多个对应的传输电路，并从一个或多个接收电路接收一组或多组串行信号，并将串行信号转换成并行信号。

    Sonet system having multiple slots providing multiple services from any slot
    6.
    发明授权
    Sonet system having multiple slots providing multiple services from any slot 有权
    Sonet系统具有多个插槽，可从任何插槽提供多种服务

    公开(公告)号：US06804248B1

    公开(公告)日：2004-10-12

    申请号：US09661544

    申请日：2000-09-14

    申请人： Sunil Tomar ,  Peter A. Reali ,  Yogendra S. Dhanik ,  Srinivasarao Neelamraju

    发明人： Sunil Tomar ,  Peter A. Reali ,  Yogendra S. Dhanik ,  Srinivasarao Neelamraju

    IPC分类号： H04L1228

    CPC分类号： H04J3/1617 ,  H04J2203/0012 ,  H04J2203/0026

    摘要： An electronic system includes a backplane, a first plurality of slots coupled to the backplane, the first plurality of slots having a first electrical interface to be coupled to electrical circuit cards of a first type, wherein the electrical circuit cards of the first type receive network data and convert the network data to SONET formatted data, and a second plurality of slots coupled to the backplane, the second plurality of slots having a second electrical interface to electrical circuit cards of a second type. The backplane routes data signals between the first plurality of slots and the second plurality of slots.

    摘要翻译： 电子系统包括背板，耦合到背板的第一多个狭槽，第一多个狭槽具有要耦合到第一类型的电路卡的第一电接口，其中第一类型接收网络的电路卡 数据并将网络数据转换成SONET格式的数据，以及耦合到背板的第二多个时隙，第二多个时隙具有与第二类型的电路卡的第二电接口。 背板在第一多个时隙和第二多个时隙之间路由数据信号。

    Methods and apparatuses for jitter protection in an integrated circuit receiving an external synchronization signal
    7.
    发明授权
    Methods and apparatuses for jitter protection in an integrated circuit receiving an external synchronization signal 有权
    接收外部同步信号的集成电路中的抖动保护方法和装置

    公开(公告)号：US06597214B1

    公开(公告)日：2003-07-22

    申请号：US09661495

    申请日：2000-09-14

    申请人： Shashij Singh ,  Sunil Tomar

    发明人： Shashij Singh ,  Sunil Tomar

    IPC分类号： H03L706

    CPC分类号： H04J3/22 ,  H04J3/0685

    摘要： A clock signal is received. A synchronization signal is compared to the clock signal to determine whether the synchronization signal is asserted within a predetermined period of time with respect to clock signal cycles. The synchronization signal assertion is used to synchronize a circuit to an external event, if the synchronization signal assertion is received within the predetermined period of time. If the synchronization signal assertion is not received within the predetermined period of time the circuit is not synchronized.

    摘要翻译： 接收时钟信号。 将同步信号与时钟信号进行比较，以确定同步信号是否在相对于时钟信号周期的预定时间段内被断言。 如果在预定时间段内接收到同步信号断言，则同步信号断言用于将电路同步到外部事件。 如果在预定时间段内没有接收到同步信号断言，则电路不同步。