公开(公告)号：US08837571B1

公开(公告)日：2014-09-16

申请号：US13958395

申请日：2013-08-02

申请人： Altera Corporation

发明人： Yanjing Ke ,  Thungoc M Tran ,  Weiqi Ding ,  Jie Shen ,  Xiong Liu ,  Sangeeta Raman ,  Peng Li

IPC分类号： H03K5/159 ,  H04L27/01

CPC分类号： H04L25/03057 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/0337 ,  H04L2025/03356

摘要： One embodiment relates to a receiver with both decision feedback equalization and on-die instrumentation. A clock data recovery loop obtains a recovered clock signal from an input signal, and a first sampler, which is triggered by the recovered clock signal, generates a recovered data signal from the input signal. A phase interpolator receives the recovered clock signal and generates a phase-interpolated clock signal. A second sampler is triggered by the recovered clock signal in a decision feedback equalization mode and by the phase-interpolated clock signal in an on-die instrumentation mode. Other embodiments and features are also disclosed.

摘要翻译： 一个实施例涉及具有判决反馈均衡和在线仪器的接收机。 时钟数据恢复循环从输入信号获得恢复的时钟信号，并且由恢复的时钟信号触发的第一采样器从输入信号产生恢复的数据信号。 相位内插器接收恢复的时钟信号并产生相位插值时钟信号。 第二取样器由判定反馈均衡模式中的恢复的时钟信号和在片上仪器模式下的相位插值时钟信号触发。 还公开了其它实施例和特征。