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公开(公告)号：US20180091181A1
公开(公告)日：2018-03-29
申请号：US15831150
申请日：2017-12-04
申请人： Altera Corporation
发明人： Donald Alderrou , Peng Li , Weiqi Ding
IPC分类号： H04B1/38 , H04L27/01 , H04B17/309
CPC分类号： H04B1/38 , H04B17/309 , H04L25/03343 , H04L25/03885 , H04L27/01
摘要： One embodiment relates to a method of automated adaptation of a transmitter equalizer. A multi-dimensional search space of tap settings for the transmitter equalizer is divided into multiple single-dimensional search spaces, each single-dimensional search space being associated with a single tap of the transmitter equalizer. The multiple single-dimensional search spaces are searched in series, and a tap for a single-dimensional search space is set before searching a next single-dimensional search space. Another embodiment relates to a transceiver with adaptation circuitry configured to perform this method. Other embodiments, aspects, and features are also disclosed.
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公开(公告)号：US20150180683A1
公开(公告)日：2015-06-25
申请号：US14633080
申请日：2015-02-26
申请人： ALTERA CORPORATION
发明人： Weiqi Ding , Mengchi Lui , Wilson Wong , Sergey Y. Shumarayev
CPC分类号： H04L25/03885 , H04L7/0054 , H04L25/03019 , H04L25/03878
摘要： Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.
摘要翻译： 用于接收高速串行数据信号（例如，具有在约10Gpbs及更高的范围内的比特率）的电路包括仅具有两个串联连接级的两级连续时间线性均衡器。 可以提供相位检测器电路用于接收均衡器的串行输出，并将该输出中的连续比特对转换为连续并行形式的位对。 可以提供进一步的解复用电路以将并行形式位对的连续组分解成最终并行位组，在位数（例如，64个并行位）方面可能相当大。 本发明的另一方面涉及用于从相对大的并行数据比特组相对于高速串行数据输出信号有效地进行反向的多路复用器电路。
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公开(公告)号：US08798127B2
公开(公告)日：2014-08-05
申请号：US13678163
申请日：2012-11-15
申请人： Altera Corporation
发明人： Weiqi Ding , Wei Li , Sergey Shumarayev
CPC分类号： H04L25/0274 , H04L25/03885 , H04L25/14
摘要： Disclosed are apparatus and methods for adaptive receiver delay equalization. One embodiment relates to a method for adaptive receiver delay equalization. Filtered positive and negative polarity signals are generated by a first variable-delay filter and a second variable-delay filter, respectively. A delay difference is determined between the filtered positive and negative polarity signals, and a skew-indication signal is generated based on the delay difference. A delay control signal is generated based on the skew-indication signal, and the delay control signal is sent to at least one of the first and second variable-delay filters. Other embodiments and features are also disclosed.
摘要翻译： 公开了用于自适应接收机延迟均衡的装置和方法。 一个实施例涉及一种用于自适应接收机延迟均衡的方法。 过滤的正极性和负极性信号分别由第一可变延迟滤波器和第二可变延迟滤波器产生。 在滤波的正极性和负极性信号之间确定延迟差，并且基于延迟差产生偏斜指示信号。 基于偏斜指示信号产生延迟控制信号，并且将延迟控制信号发送到第一和第二可变延迟滤波器中的至少一个。 还公开了其它实施例和特征。
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4.发明授权Apparatus and methods for detection and correction of transmitter duty cycle distortion 有权用于检测和校正发射机占空比失真的装置和方法公开(公告)号：US08644440B1
公开(公告)日：2014-02-04
申请号：US13900279
申请日：2013-05-22
申请人： Altera Corporation
发明人： Weiqi Ding
IPC分类号： H04L7/00
CPC分类号： H04L7/00 , H03K5/1565
摘要： One embodiment relates to an integrated circuit which includes a transmitter buffer circuit, a duty cycle distortion (DCD) detector, correction logic, and a duty cycle adjuster. The DCD detector is configured to selectively couple to the serial output of the transmitter buffer circuit. The correction logic is configured to generate control signals based on the output of the DCD detector. The duty cycle adjuster is configured to adjust a duty cycle of the serial input signal based on the control signals. Another embodiment relates to a method of correcting duty cycle distortion in a transmitter. Other embodiments and features are also disclosed.
摘要翻译： 一个实施例涉及一种集成电路，其包括发射机缓冲电路，占空比失真（DCD）检测器，校正逻辑和占空比调节器。 DCD检测器被配置为选择性地耦合到发射机缓冲电路的串行输出。 校正逻辑被配置为基于DCD检测器的输出产生控制信号。 占空比调整器被配置为基于控制信号调整串行输入信号的占空比。 另一实施例涉及一种校正发射机中占空比失真的方法。 还公开了其它实施例和特征。
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公开(公告)号：US10212498B1
公开(公告)日：2019-02-19
申请号：US15470778
申请日：2017-03-27
申请人： ALTERA CORPORATION
摘要： Systems and methods are provided to improve flexibility of optical signal transmission between integrated circuit devices, and more specifically data utilization circuits. More specifically, the integrated circuit devices may include a data utilization circuit communicatively coupled to a field programmable optical array (FPOA). In some embodiments, the FPOA may convert an electrical signal received from the data utilization to an optical signal, route the optical signal to an optical channel, and multiplex the optical signal with other optical signals routed to the optical channel. Additionally or alternatively, the FPOA may de-multiplex a multiplexed optical signal based on wavelength, route an optical signal included in the multiplexed optical signal to an electrical channel, convert the optical signal into an electrical signal, and output the electrical signal to the data utilization circuit via an electrical channel. In some embodiments, the FPOA may improve flexibility by performing such functions without reconfiguring the data utilization circuit.
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公开(公告)号：US08958512B1
公开(公告)日：2015-02-17
申请号：US14057955
申请日：2013-10-18
申请人： Altera Corporation
发明人： Weiqi Ding , Wei Li
CPC分类号： H04L25/03057 , H04L25/03885 , H04L25/061 , H04L2025/03745
摘要： One embodiment relates to a method of adapting a receiver for equalization of an input data signal. A variable gain amplifier (VGA) loop adapts a VGA circuit using an initial threshold voltage so as to adjust a VGA gain setting to regulate a data amplitude feeding into a decision feedback equalization (DFE) circuit. In addition, the DFE adaptation loop may adapt the DFE circuit using the initial threshold voltage. When the adaptation of the VGA is done, then the VGA gain setting is frozen and adaptation of the threshold voltage may be performed by a threshold adaptation loop. Another embodiment relates to a system which includes a DFE adaptation circuit module, a CTLE adaptation circuit module, and a threshold adaptation circuit module that adapts a threshold voltage that is fed to the DFE adaptation circuit and the CTLE adaptation circuit. Other embodiments and features are also disclosed.
摘要翻译： 一个实施例涉及一种使接收机适配输入数据信号的均衡的方法。 可变增益放大器（VGA）环路使用初始阈值电压适配VGA电路，以便调整VGA增益设置以调节馈送到判决反馈均衡（DFE）电路中的数据幅度。 此外，DFE适配环路可以使用初始阈值电压来适应DFE电路。 当VGA的自适应完成时，VGA增益设置被冻结，阈值电压的调整可以由阈值适配环路来执行。 另一实施例涉及一种系统，其包括DFE适配电路模块，CTLE适配电路模块和适应馈送到DFE适配电路和CTLE自适应电路的阈值电压的阈值自适应电路模块。 还公开了其它实施例和特征。
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公开(公告)号：US08922264B1
公开(公告)日：2014-12-30
申请号：US13871812
申请日：2013-04-26
申请人： Altera Corporation
发明人： Yan Chong , Warren Nordyke , Sean Shau-Tu Lu , Weiqi Ding
CPC分类号： H03L7/00
摘要： Clock alignment circuitry may include phase comparator circuitry with a first input terminal that receives as first clock signal from a first clock tree and a second input terminal that receives a second clock signal from a second clock tree. The phase comparator circuitry may compare the first and second clock signals and generate different control signals based on the first and second clock signals. The integrated circuit may further include phase interpolator circuitry that generates an output clock signal based on at least one of the control signals received from the phase comparator circuitry. Edges of the generated output clock signal may align with edges of either the first clock signal or the second clock signal.
摘要翻译： 时钟对准电路可以包括相位比较器电路，其具有从第一时钟树接收第一时钟信号的第一输入端和从第二时钟树接收第二时钟信号的第二输入端。 相位比较器电路可以比较第一和第二时钟信号，并且基于第一和第二时钟信号产生不同的控制信号。 集成电路还可以包括基于从相位比较器电路接收的控制信号中的至少一个产生输出时钟信号的相位插值器电路。 产生的输出时钟信号的边沿可以与第一时钟信号或第二时钟信号的边缘对准。
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公开(公告)号：US08837571B1
公开(公告)日：2014-09-16
申请号：US13958395
申请日：2013-08-02
申请人： Altera Corporation
发明人： Yanjing Ke , Thungoc M Tran , Weiqi Ding , Jie Shen , Xiong Liu , Sangeeta Raman , Peng Li
CPC分类号： H04L25/03057 , H04L7/0025 , H04L7/0087 , H04L7/0337 , H04L2025/03356
摘要： One embodiment relates to a receiver with both decision feedback equalization and on-die instrumentation. A clock data recovery loop obtains a recovered clock signal from an input signal, and a first sampler, which is triggered by the recovered clock signal, generates a recovered data signal from the input signal. A phase interpolator receives the recovered clock signal and generates a phase-interpolated clock signal. A second sampler is triggered by the recovered clock signal in a decision feedback equalization mode and by the phase-interpolated clock signal in an on-die instrumentation mode. Other embodiments and features are also disclosed.
摘要翻译： 一个实施例涉及具有判决反馈均衡和在线仪器的接收机。 时钟数据恢复循环从输入信号获得恢复的时钟信号，并且由恢复的时钟信号触发的第一采样器从输入信号产生恢复的数据信号。 相位内插器接收恢复的时钟信号并产生相位插值时钟信号。 第二取样器由判定反馈均衡模式中的恢复的时钟信号和在片上仪器模式下的相位插值时钟信号触发。 还公开了其它实施例和特征。
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公开(公告)号：US09654123B1
公开(公告)日：2017-05-16
申请号：US15138749
申请日：2016-04-26
申请人： ALTERA CORPORATION
CPC分类号： H03L7/23 , G06F1/10 , H03L7/0807 , H03L7/183 , H03L7/197 , H03L7/1974 , H04L7/0331
摘要： One embodiment relates to an integrated circuit including multiple PMA modules, a plurality of multiple-purpose PLLs, multiple reference clock signal inputs, and a programmable clock network. Another embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit including a first strip of PLL circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. Other embodiments and features are also disclosed.
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公开(公告)号：US09608728B1
公开(公告)日：2017-03-28
申请号：US14163780
申请日：2014-01-24
申请人： ALTERA CORPORATION
IPC分类号： H04B10/00 , H04B10/2575 , H04Q11/00 , H04J14/00
CPC分类号： H04B10/2575 , H04B10/801 , H04Q11/0005
摘要： Systems and methods are provided to improve flexibility of optical signal transmission between integrated circuit devices, and more specifically data utilization circuits. More specifically, the integrated circuit devices may include a data utilization circuit communicatively coupled to a field programmable optical array (FPOA). In some embodiments, the FPOA may convert an electrical signal received from the data utilization to an optical signal, route the optical signal to an optical channel, and multiplex the optical signal with other optical signals routed to the optical channel. Additionally or alternatively, the FPOA may de-multiplex a multiplexed optical signal based on wavelength, route an optical signal included in the multiplexed optical signal to an electrical channel, convert the optical signal into an electrical signal, and output the electrical signal to the data utilization circuit via an electrical channel. In some embodiments, the FPOA may improve flexibility by performing such functions without reconfiguring the data utilization circuit.
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