公开(公告)号：US06434704B1

公开(公告)日：2002-08-13

申请号：US09375118

申请日：1999-08-16

申请人： Alvar Dean ,  David C. Garrett ,  Mircea Stan

发明人： Alvar Dean ,  David C. Garrett ,  Mircea Stan

IPC分类号： G06F132

CPC分类号： G06F17/5045 ,  G06F1/10

摘要： Methods are provided for improving the efficiency of clock gating within low power clock trees. In a first aspect, a correlation level between a plurality of clock gating signals and their corresponding gates which gate a source clock is determined. The clock gating signals and their corresponding gates are combined into a single clock gating signal and a single corresponding gate if a preselected level of correlation exists therebetween. In a second aspect, an area overlap is determined for a plurality of sinks, and one of the gated drovers of the sinks is removed. The sinks of the removed gated driver then are connected to a remaining gated driver driven by a single clock gating signal and a single corresponding gate. In a third aspect, physically proximate sink clusters are rewired to generate a pure clock gating group within each sink cluster if rewiring the clusters increases wiring length by less than a predetermined amount. In a fourth aspect, a clock gating group is selected and the power dissipation is computed for all sinks within the selected group assuming all the sinks therein are wired without clock gating. The power dissipation also is computed assuming all the sinks therein are gated. If the power dissipation for all sinks within the selected group is reduced by individually wiring the sinks therein, the group is ungated. A computer program product also is provided having a computer readable medium with means for performing the first, second, third and/or fourth aspects of the invention.

摘要翻译： 提供了用于提高低功率时钟树中时钟门控效率的方法。 在第一方面，确定多个时钟选通信号与其对源时钟的相应门之间的相关电平。 时钟选通信号及其对应的门被组合成单个时钟门控信号和单个相应的门，如果它们之间存在预选的相关级别。 在第二方面，确定了多个接收器的区域重叠，并且去除了接收器的门控拖动中的一个。 然后，去除的门控驱动器的接收器连接到由单个时钟门控信号和单个相应门驱动的剩余门控驱动器。 在第三方面，重新布线物理上靠近的宿簇，以在每个宿簇内产生纯时钟选通组，如果重新布线，群集将布线长度增加小于预定量。 在第四方面中，选择时钟门控组，并且对于所选择的组中的所有接收器，计算所有接收器的功耗，假定其中的所有接收器没有时钟选通而被连接。 假定其中的所有汇槽均为门控，则计算功耗。 如果通过单独接线其中的接收器来降低所选组内的所有接收器的功耗，则该组是非门控的。 还提供了一种具有计算机可读介质的计算机程序产品，该计算机可读介质具有用于执行本发明的第一，第二，第三和/或第四方面的装置。

公开(公告)号：US20060038602A1

公开(公告)日：2006-02-23

申请号：US11255707

申请日：2005-10-21

申请人： Anthony Bonaccio ,  John Cohn ,  Alvar Dean ,  Amir Farrahi ,  David Hathaway ,  Sebastian Ventrone

发明人： Anthony Bonaccio ,  John Cohn ,  Alvar Dean ,  Amir Farrahi ,  David Hathaway ,  Sebastian Ventrone

IPC分类号： G06F1/04

CPC分类号： G06F1/10

摘要： A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.

公开(公告)号：US20080091994A1

公开(公告)日：2008-04-17

申请号：US11955433

申请日：2007-12-13

申请人： Alvar Dean ,  Sebastian Ventrone

发明人： Alvar Dean ,  Sebastian Ventrone

IPC分类号： G01R31/28

CPC分类号： G01R31/2893 ,  G01R1/0408 ,  G01R31/318505 ,  G01R31/31932

摘要： A test board includes a plurality of sockets for connection to a plurality of integrated circuit chips to be tested. A test control device on the board turns on at least one test engine for testing the plurality of chips simultaneously. A checking circuit verifies the functionality of each chip by comparing outputs of chips with each other or with a golden chip. Failing Chips are disconnected from further testing and passing or failing chips are recorded.

摘要翻译： 测试板包括用于连接到待测试的多个集成电路芯片的多个插座。 板上的测试控制装置打开至少一个测试引擎，同时测试多个芯片。 检查电路通过将芯片的输出相互比较或与金色芯片进行比较来验证每个芯片的功能。 失败的芯片与进一步的测试断开连接，并记录通过或失败的芯片。

公开(公告)号：US20080074147A1

公开(公告)日：2008-03-27

申请号：US11952544

申请日：2007-12-07

申请人： John Cohn ,  Alvar Dean ,  Amir Farrahi ,  David Hathaway ,  Thomas Lepsic ,  Jagannathan Narasimhan ,  Scott Tetreault ,  Sebastian Ventrone

发明人： John Cohn ,  Alvar Dean ,  Amir Farrahi ,  David Hathaway ,  Thomas Lepsic ,  Jagannathan Narasimhan ,  Scott Tetreault ,  Sebastian Ventrone

IPC分类号： H03K19/00 ,  G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5022 ,  G06F17/5077

摘要： An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability φSD per clock cycle that is no less than a pre-selected minimum same-direction switching probability φSD,MIN or has an opposite-direction switching probability φOD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability φOD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.

摘要翻译： 一种用于设计电气布线结构的电气布线结构和计算机系统。 电气配线结构包括电线对。 线对包括第一线和第二线。 第二根电线被预定为三态。 线对具有不小于预先选择的最小相同方向切换概率phi，SD，MIN或/或具有相同方向的切换概率，每时钟周期 每个时钟周期的相反方向切换概率Φ不小于预先选择的最小相对方向切换概率φi，MIN 。 第一线和第二线满足至少一个数学关系，其涉及公平和平坦，其中，W SPACING 被定义为 第一线和第二线，以及公共被定义为第一线和第二线的公共行程长度。

公开(公告)号：US20050262463A1

公开(公告)日：2005-11-24

申请号：US11176712

申请日：2005-07-07

申请人： John Cohn ,  Alvar Dean ,  Amir Farrahi ,  David Hathaway ,  Thomas Lepsic ,  Jagannathan Narasimhan ,  Scott Tetreault ,  Sebastian Ventrone

发明人： John Cohn ,  Alvar Dean ,  Amir Farrahi ,  David Hathaway ,  Thomas Lepsic ,  Jagannathan Narasimhan ,  Scott Tetreault ,  Sebastian Ventrone

IPC分类号： G06F17/50 ,  H01L21/82 ,  G06F9/45 ,  H03K19/0175

CPC分类号： G06F17/5072 ,  G06F17/5022 ,  G06F17/5077

摘要： An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.

摘要翻译： 电气布线结构及其设计方法。 该方法识别具有第一线和第二线的至少一个线对。 第二根线已经是三态的，也可以是三态的。 线对可以具有不小于预定或用户选择的最小相同方向切换概率的每时钟周期的相同方向的切换概率。 或者，线对可以具有不小于预定或用户选择的最小相反方向切换概率的每时钟周期的相反方向切换概率。 第一线和第二线满足至少一个数学关系，涉及：第一线和第二线之间的间隔; 以及第一线和第二线的公共行程长度。

公开(公告)号：US06269468B1

公开(公告)日：2001-07-31

申请号：US09260453

申请日：1999-03-02

申请人： Alvar Dean ,  Patrick E. Perry ,  Sebastian Ventrone

发明人： Alvar Dean ,  Patrick E. Perry ,  Sebastian Ventrone

IPC分类号： G06F1750

CPC分类号： G06F17/505 ,  G06F2217/78

摘要： A logic circuit device and circuit design methodology includes a “split-book” logic circuit design having different active device sizes with outputs for connections to both critical and non-critical digital circuit paths. By using “split” book designs with separate input and output stages, better silicon utilization, power optimization, and performance results. This is because each split book is designed with multiple output buffers that may be configured to optimally drive critical and non-critical paths. During the power/performance optimization phase of the design, timing critical paths of the design are first identified, with each path being optimized on its own basis. First the input stage of the strand may be improved with a stronger drive on the input port of the book. Only the input port that has been linked to a critical path is updated. The other input pins are left at their default setting. Then, the output buffers may then be connected together according to criticality of the path and net capacitive load they are driving. Different split book input/output circuit combinations may be attempted during the design phase until an optimal tradeoff between power optimization and performance is reached.

摘要翻译： 逻辑电路器件和电路设计方法包括具有不同有源器件尺寸的“分离式”逻辑电路设计，其输出用于连接关键和非关键数字电路路径。 通过使用具有独立输入和输出级的“拆分”书籍设计，更好的硅利用率，功耗优化和性能结果。 这是因为每个拆分书都设计有多个输出缓冲区，可以配置为最佳地驱动关键路径和非关键路径。 在设计的功率/性能优化阶段期间，首先确定设计的时序关键路径，每个路径都以其自身为基础进行优化。 首先，可以通过在书的输入端口上的更强的驱动来改进链的输入阶段。 仅链接到关键路径的输入端口已更新。 其他输入引脚保持默认设置。 然后，输出缓冲器然后可以根据它们正在驱动的路径和净电容负载的关键性被连接在一起。 可以在设计阶段尝试不同的分页输入/输出电路组合，直到达到功率优化和性能之间的最佳权衡。