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公开(公告)号：US07570267B2
公开(公告)日：2009-08-04
申请号：US10934249
申请日：2004-09-03
申请人： Amar Patel , Charles N. Boyd , David R. Blythe , Jeff M. J. Noyle , Michael A. Toelle , Stephen Harry Wright
发明人： Amar Patel , Charles N. Boyd , David R. Blythe , Jeff M. J. Noyle , Michael A. Toelle , Stephen Harry Wright
CPC分类号： G06T15/005
摘要： An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming. By using the enhanced graphics pipeline, the programmer can optimize the usage of the hardware in the pipeline, program vertex, line or triangle topologies altogether rather than each vertex alone, and read any calculated data from memory where the pipeline can output the calculated information.
摘要翻译： 提供了增强的图形流水线，其使公共核心硬件能够执行图形流水线的不同组件，由流水线中的组件包括线和三角形的原语的可编程性，以及在呈现与图形显示之间的流输出 数据在管道中。 编程人员不必优化代码，因为通用核心将平衡所需功能的负载，并在通用核心硬件上动态分配这些指令。 程序员可以使用算法编程原语，以通过用线和三角形进行拓扑替换来简化所有顶点计算。 程序员获取计算的输出数据，并在渲染之前或期间读取它们。 因此，程序员在编程中具有更大的灵活性。 通过使用增强型图形管线，程序员可以优化管道中硬件的使用，程序顶点，线或三角形拓扑，而不是单独使用每个顶点，并从管道可以输出计算的信息的内存读取任何计算的数据。
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公开(公告)号：US09064334B2
公开(公告)日：2015-06-23
申请号：US13152452
申请日：2011-06-03
申请人： Amar Patel , Charles N. Boyd , David R. Blythe , Jeff M. J. Noyle , Michael A. Toelle , Stephen Harry Wright
发明人： Amar Patel , Charles N. Boyd , David R. Blythe , Jeff M. J. Noyle , Michael A. Toelle , Stephen Harry Wright
摘要： An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming. By using the enhanced graphics pipeline, the programmer can optimize the usage of the hardware in the pipeline, program vertex, line or triangle topologies altogether rather than each vertex alone, and read any calculated data from memory where the pipeline can output the calculated information.
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公开(公告)号：US07978205B1
公开(公告)日：2011-07-12
申请号：US10933850
申请日：2004-09-03
申请人： Amar Patel , Charles N. Boyd , David R. Blythe , Jeff M. J. Noyle , Michael A. Toelle , Stephen Harry Wright
发明人： Amar Patel , Charles N. Boyd , David R. Blythe , Jeff M. J. Noyle , Michael A. Toelle , Stephen Harry Wright
IPC分类号： G09G5/00
摘要： An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming. By using the enhanced graphics pipeline, the programmer can optimize the usage of the hardware in the pipeline, program vertex, line or triangle topologies altogether rather than each vertex alone, and read any calculated data from memory where the pipeline can output the calculated information.
摘要翻译： 提供了增强的图形流水线，其使公共核心硬件能够执行图形流水线的不同组件，由流水线中的组件包括线和三角形的原语的可编程性，以及在呈现与图形显示之间的流输出 数据在管道中。 编程人员不必优化代码，因为通用核心将平衡所需功能的负载，并在通用核心硬件上动态分配这些指令。 程序员可以使用算法编程原语，以通过用线和三角形进行拓扑替换来简化所有顶点计算。 程序员获取计算的输出数据，并在渲染之前或期间读取它们。 因此，程序员在编程中具有更大的灵活性。 通过使用增强型图形管线，程序员可以优化管道中硬件的使用，程序顶点，线或三角形拓扑，而不是单独使用每个顶点，并从管道可以输出计算的信息的内存读取任何计算的数据。
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公开(公告)号：US07671862B1
公开(公告)日：2010-03-02
申请号：US10934241
申请日：2004-09-03
申请人： Amar Patel , Charles N. Boyd , David R. Blythe , Jeff M. J. Noyle , Michael A. Toelle , Stephen Harry Wright
发明人： Amar Patel , Charles N. Boyd , David R. Blythe , Jeff M. J. Noyle , Michael A. Toelle , Stephen Harry Wright
摘要： An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming. By using the enhanced graphics pipeline, the programmer can optimize the usage of the hardware in the pipeline, program vertex, line or triangle topologies altogether rather than each vertex alone, and read any calculated data from memory where the pipeline can output the calculated information.
摘要翻译： 提供了增强的图形流水线，其使公共核心硬件能够执行图形流水线的不同组件，由流水线中的组件包括线和三角形的原语的可编程性，以及在呈现与图形显示之间的流输出 数据在管道中。 编程人员不必优化代码，因为通用核心将平衡所需功能的负载，并在通用核心硬件上动态分配这些指令。 程序员可以使用算法编程原语，以通过用线和三角形进行拓扑替换来简化所有顶点计算。 程序员获取计算的输出数据，并在渲染之前或期间读取它们。 因此，程序员在编程中具有更大的灵活性。 通过使用增强型图形管线，程序员可以优化管道中硬件的使用，程序顶点，线或三角形拓扑，而不是单独使用每个顶点，并从管道可以输出计算的信息的内存中读取任何计算的数据。
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公开(公告)号：US20110234592A1
公开(公告)日：2011-09-29
申请号：US13152452
申请日：2011-06-03
申请人： Amar Patel , Charles N. Boyd , David R. Blythe , Jeff M.J. Noyle , Michael A. Toelle , Stephen Harry Wright
发明人： Amar Patel , Charles N. Boyd , David R. Blythe , Jeff M.J. Noyle , Michael A. Toelle , Stephen Harry Wright
摘要： An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming. By using the enhanced graphics pipeline, the programmer can optimize the usage of the hardware in the pipeline, program vertex, line or triangle topologies altogether rather than each vertex alone, and read any calculated data from memory where the pipeline can output the calculated information.
摘要翻译： 提供了增强的图形流水线，其使公共核心硬件能够执行图形流水线的不同组件，由流水线中的组件包括线和三角形的原语的可编程性，以及在呈现与图形显示之间的流输出 数据在管道中。 编程人员不必优化代码，因为通用核心将平衡所需功能的负载，并在通用核心硬件上动态分配这些指令。 程序员可以使用算法编程原语，以通过用线和三角形进行拓扑替换来简化所有顶点计算。 程序员获取计算的输出数据，并在渲染之前或期间读取它们。 因此，程序员在编程中具有更大的灵活性。 通过使用增强型图形管线，程序员可以优化管道中硬件的使用，程序顶点，线或三角形拓扑，而不是单独使用每个顶点，并从管道可以输出计算的信息的内存读取任何计算的数据。
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6.发明授权Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques 有权将算法元素下载到协处理器的系统和方法以及相应的技术公开(公告)号：US08274517B2
公开(公告)日：2012-09-25
申请号：US10986586
申请日：2004-11-12
申请人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
发明人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
摘要翻译： 提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。 对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。 本发明允许对下载到协处理器的程序的运行时预测流控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在 顶点着色器提供输入到顶点着色器的顶点着色器的分频，可选地支持流模值，在像素着色器上提供寄存器存储元素，并且与表示像素的“面”关联的存储相关联的接口提供顶点 着色器和像素着色器，具有更多的片上寄存器存储，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。
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7.发明授权Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques 有权将算法元素下载到协处理器的系统和方法以及相应的技术公开(公告)号：US08823718B2
公开(公告)日：2014-09-02
申请号：US10987686
申请日：2004-11-12
申请人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
发明人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
摘要翻译： 提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。 对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。 本发明允许对下载到协处理器的程序的运行时预测流程控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在 顶点着色器提供输入到顶点着色器的顶点着色器的分频，可选地支持流模值，在像素着色器上提供寄存器存储元素，并且与表示像素的“面”关联的存储相关联的接口提供顶点 着色器和像素着色器，具有更多的片上寄存器存储，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。
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8.发明授权Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques 有权将算法元素下载到协处理器的系统和方法以及相应的技术公开(公告)号：US08305381B2
公开(公告)日：2012-11-06
申请号：US12112676
申请日：2008-04-30
申请人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
发明人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
摘要翻译： 提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。 对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。 本发明允许对下载到协处理器的程序的运行时预测流程控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在 顶点着色器提供输入到顶点着色器的顶点着色器的分频，其中可选地支持流模数值，在像素着色器上提供寄存器存储元件，并且与表示像素的面相关联的存储相关联的接口，提供顶点着色器和 具有更多片上寄存器存储的像素着色器，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。
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公开(公告)号：US07978197B2
公开(公告)日：2011-07-12
申请号：US10987144
申请日：2004-11-12
申请人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
发明人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
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10.发明申请SYSTEMS AND METHODS FOR DOWNLOADING ALGORITHMIC ELEMENTS TO A COPROCESSOR AND CORRESPONDING TECHNIQUES 有权将算法元素下载到协处理器和相应技术的系统和方法公开(公告)号：US20080198169A1
公开(公告)日：2008-08-21
申请号：US12112676
申请日：2008-04-30
申请人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
发明人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
IPC分类号： G06T1/00
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
摘要翻译： 提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。 对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。 本发明允许对下载到协处理器的程序的运行时预测流程控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在 顶点着色器提供输入到顶点着色器的顶点着色器的分频，可选地支持流模值，在像素着色器上提供寄存器存储元素，并且与表示像素的“面”关联的存储相关联的接口提供顶点 着色器和像素着色器，具有更多的片上寄存器存储，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。
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