公开(公告)号：US10955472B1

公开(公告)日：2021-03-23

申请号：US16444917

申请日：2019-06-18

Applicant: Amazon Technologies, Inc.

Inventor： Dan Trock ,  Valentin Bader ,  Shlomi Vilozny ,  Shimon Rahamim ,  Danny Sapoznikov ,  Yair Armoza ,  Itai Avron

IPC: G01R31/3177 ,  G01R31/317

Abstract: An integrated circuit includes first and second cores. Each core has a power-switchable portion in a first power domain in which an operating power is turned on or off in response to a power control signal. The first power domain includes a first scan chain, and the first power domain also includes a plurality of outputs. Each core also includes an always-on portion in a second power domain in which the operating power is maintained during testing of the integrated circuit. The second power domain also has a second scan chain. The second power domain further includes respective isolation gates coupled to the plurality of outputs of the first power domain, and the second scan chain includes a respective wrapper cell coupled to some isolation gates. The integrated circuit is configured to power off and isolate the power-switchable portion in the first power domain based on a scan test result.

公开(公告)号：US10990739B1

公开(公告)日：2021-04-27

申请号：US16366717

申请日：2019-03-27

Applicant: Amazon Technologies, Inc.

Inventor： Dan Trock ,  Sergey Kleyman ,  Danny Sapoznikov

IPC: G06F30/392 ,  H01L23/498 ,  H01L23/00

Abstract: An integrated circuit device includes multiple circuit tiles disposed in a tiled arrangement in a circuit block between a first boundary and a second boundary. Each circuit tile is an instance of a circuit cell having a first edge and a second edge. The circuit cell has a scan channel circuit that includes a configurable scan channel switch and scan channels extending between the first edge and the second edge of the circuit cell through the configurable scan channel switch. Respective scan channels in the multiple circuit tiles are joined together and extend between the first boundary and the second boundary of the block of tiled arrangement. Each circuit tile can be configured to receive scan-in test data through a scan channel from either the first boundary or the second boundary, and to output scan-out result data of the circuit tile through a scan channel to either the first boundary or the second boundary.