公开(公告)号：US11687576B1

公开(公告)日：2023-06-27

申请号：US17466899

申请日：2021-09-03

Applicant: Amazon Technologies, Inc.

Inventor： Noam Katz ,  Mohammad Naghshvar ,  Harshal Dilip Wanjari

IPC: H04N21/488 ,  G06F16/34

CPC classification number: G06F16/345 ,  H04N21/4882

Abstract: Summaries of media programs that are in progress are generated based on content of the media programs that has already been transmitted to listeners or viewers. The content is transcribed into text, and contextual features regarding the media program such as topics, identities of speakers or interactions received from listeners are identified. The transcribed content and the contextual features are provided as multi-modal inputs to a model that is trained to generate a summary of the media program in response to such inputs. Summaries of media programs that are then in progress are transmitted to devices of listeners who may be interested in joining one of the media programs and displayed in a menu or user interface or announced to the listeners.

公开(公告)号：US11967964B1

公开(公告)日：2024-04-23

申请号：US17709939

申请日：2022-03-31

Applicant: Amazon Technologies, Inc.

Inventor： Noam Katz ,  Said Bshara ,  Erez Izenberg ,  Noam Attias

IPC: H03L7/10 ,  G11C7/10 ,  H03L7/083 ,  H03L7/199

CPC classification number: H03L7/103 ,  G11C7/1039 ,  H03L7/083 ,  H03L7/199

Abstract: A clock disciplining scheme uses a pulse per second (PPS) signal that is distributed throughout a network to coordinate timing. In determining the time, jitter can occur due to latency between detection of the PPS signal and a software interrupt generated there from. This jitter affects the accuracy of the clock disciplining process. To eliminate the jitter, extra hardware is used to capture when the PPS signal occurred relative to a hardware clock counter associated with the clock disciplining software. In one embodiment, the extra hardware can be a sampling logic, which captures a state of a hardware clock counter upon PPS detection. In another embodiment, the extra hardware can initiate a counter that calculates a delay by the clock disciplining software in reading the hardware clock counter. The disciplining software can then subtract the calculated delay from a hardware clock counter to obtain the original PPS signal.

公开(公告)号：US11868292B1

公开(公告)日：2024-01-09

申请号：US17656710

申请日：2022-03-28

Applicant: Amazon Technologies, Inc.

Inventor： Lev Vaskevich ,  Noam Katz

IPC: G06F13/366 ,  G06F9/50

CPC classification number: G06F13/366 ,  G06F9/5033

Abstract: A plurality of resource requesters may be configured to consume a resource to perform a task. Each of the plurality of resource requesters can be allocated a resource budget to consume the resource to perform the task. An arbiter can select one of the plurality of resource requesters to consume the resource based on an arbitration scheme. When a resource requester is selected, the amount of resource consumed by the resource requester can be deducted from its resource budget. When the resource requester is idle for a number of cycles when selected, the corresponding resource budget can be further reduced to account for the actual amount of resource consumed and wasted by the resource requester, which can provide fairness in resource consumption over few rounds of arbitration.

公开(公告)号：US11811637B1

公开(公告)日：2023-11-07

申请号：US17456511

申请日：2021-11-24

Applicant: Amazon Technologies, Inc.

Inventor： Noam Katz ,  Amiram Lifshitz ,  Said Bshara ,  Erez Izenberg ,  Jonathan Chocron

IPC: H04L43/106 ,  H04L69/28 ,  H04L69/18

CPC classification number: H04L43/106 ,  H04L69/18 ,  H04L69/28

Abstract: To support different timestamp formats, for example, for different network protocols, an integrated circuit device is provided with a memory that is programmed with multiple instruction sets associated with multiple timestamp formats. Each of the instruction sets contains instructions to generate a timestamp according to a corresponding timestamp format. A compute circuit can generate a formatted timestamp by using a base timestamp input and executing an instruction set selected from the multiple instruction sets stored in the memory.