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1.发明授权公开(公告)号：US11036543B1
公开(公告)日：2021-06-15
申请号：US16441616
申请日：2019-06-14
Applicant: Amazon Technologies, Inc.
Inventor： Robert Charles Swanson , Christopher James BeSerra
Abstract: Systems and methods for an integrated reliability, availability, and serviceability (RAS) state machine are provided. Handling of RAS events by the Basic Input Output System (BIOS) of an integrated circuit device can result in lost processing time on the processing cores of a multi-core processor resulting from numerous system management interrupts generated by the BIOS. To reduce lost processing time, a dedicated state machine can execute instructions to handle RAS events independently of the BIOS and minimize the number of system management interrupts.
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公开(公告)号：US11487550B1
公开(公告)日：2022-11-01
申请号：US17113625
申请日：2020-12-07
Applicant: Amazon Technologies, Inc.
Inventor： Troy Lawson Bevis , Nathan Pritchard , Robert Charles Swanson , Tinghui Wang
Abstract: Approaches in accordance with various embodiments provide for the management of system event data in a computing device. In particular, various embodiments provide an intelligent persistent buffer for system event log (SEL) messages. A SEL message can be generated by system BIOS on a computing device, which can send this message over an appropriate interface to a target recipient, such as the BMC. Instead of being received directly to the BMC, however, the SEL message can be received to a logic device, such as a CPLD, that is able to analyze the message, determine that the message relates to an important system event, and can cause this message to be stored to a persistent buffer. The BMC can then subsequently request the buffered SEL message from the logic device to take an appropriate action.
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公开(公告)号：US11188407B1
公开(公告)日：2021-11-30
申请号：US16413341
申请日：2019-05-15
Applicant: Amazon Technologies, Inc.
Abstract: When a computer boots up, a Basic Input/Output System (BIOS) configures system memory to have a crash memory area within the system address map, which can be used by a processor to dump crash memory data. When an error event occurs, the processor can initiate a dump to the crash memory area. Any desired data can be placed into the crash memory area, but typical data can include a state of registers in the processor. The processor then sets a flag, such as an external pin, indicating that the crash memory data is ready to be read. The flag can be read by a secure processor, which then reads the crash memory area at normal memory access speeds using the system bus. For example, the secure processor can access the crash memory area using Direct Memory Access (DMA) reads over a PCIe system bus.
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公开(公告)号：US12135669B1
公开(公告)日：2024-11-05
申请号：US17709199
申请日：2022-03-30
Applicant: Amazon Technologies, Inc.
Inventor： Michael Moen , Darin Lee Frink , Ravi Akundi Murty , Robert Charles Swanson , Anthony Nicholas Liguori
Abstract: An interposer card and a virtualization offloading card are provided for installation in a third-party server to integrate the third-party server into a cloud service provider network. The interposer card includes a baseboard management controller that interfaces with a management console of the cloud service provider network. This allows the third-party server to be converted into a server controlled by the cloud service provider network. Additionally, the baseboard management controller of the interposer card acts as a firewall between the third-party server and a management control network of the cloud service provider network. The interposer card and the virtualization offloading card are installed in a chassis of the third-party server via an expansion slot without requiring modification of the hardware or firmware of the third-party server.
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