公开(公告)号：US11262782B2

公开(公告)日：2022-03-01

申请号：US16861915

申请日：2020-04-29

Applicant: Analog Devices, Inc.

Inventor： Devrim Aksin ,  Omid Foroudi

IPC: G05F3/26 ,  H03F3/14 ,  H03M1/12 ,  H03F3/345

Abstract: An example current mirror arrangement includes a current mirror circuit, configured to receive an input current signal at an input transistor Q1 and output a mirrored signal at an output transistor Q2. The arrangement further includes a semi-cascoding circuit that includes transistors Q3, Q4, and a two-terminal passive network. The transistor Q3 is coupled to, and forms a cascode with, the output transistor Q2. The transistor Q4 is coupled to the transistor Q3. The base/gate of the transistor Q3 is coupled to a bias voltage Vref, and the base/gate of the transistor Q4 is coupled to a bias voltage Vref1 via the two-terminal passive network. Nonlinearity of the output current from such a current mirror arrangement may be reduced by selecting appropriate impedance of the two-terminal passive network and selecting appropriate bias voltages Vref and Vref1.

公开(公告)号：US10895887B1

公开(公告)日：2021-01-19

申请号：US16724212

申请日：2019-12-21

Applicant: Analog Devices, Inc.

Inventor： Devrim Aksin ,  Omid Foroudi

IPC: G05F3/02 ,  G05F3/26

Abstract: An example current mirror arrangement includes a first portion and a second portion, each of which includes a current mirror having transistors Q1 and Q2, a buffer amplifier that has an input coupled to a base/gate terminal of Q1 and an output coupled to a base/gate terminal of Q2, a master resistor coupled to an emitter/source terminal of Q1, and a slave resistor coupled to an emitter/source terminal of Q2. Furthermore, the slave resistor of the first portion is coupled to the slave resistor of the second portion. Providing additional resistors on master and slave sides of a current mirror arrangement may advantageously allow benefiting from the use of buffers outside of a feedback loop of a current mirror while reducing the sensitivity of the current mirror arrangement to buffer offsets.

公开(公告)号：US11106233B1

公开(公告)日：2021-08-31

申请号：US16774283

申请日：2020-01-28

Applicant: Analog Devices, Inc.

Inventor： Devrim Aksin ,  Omid Foroudi

IPC: G05F3/26 ,  G05F3/16

Abstract: An example current mirror arrangement includes a current mirror circuit having an input transistor and an output transistor, where the base/gate terminal of the input transistor is coupled to its collector/drain terminal via a transistor matrix that includes a plurality of transistors. Transistors of the transistor matrix, together with the input transistor, form two parallel feedback loops, such that the input transistor is part of both loops. The first loop is a fast, low-gain loop, while the second loop is a slow, high-gain loop. At lower input frequencies, the high-gain loop may properly bias and accurately generate voltage at the base/gate terminal of the input transistor, while at higher input frequencies the fast loop may significantly extend the linear operating frequency band. Consequently, a current mirror arrangement with improvements in terms of linearity and signal bandwidth may be realized.

公开(公告)号：US11188112B2

公开(公告)日：2021-11-30

申请号：US16832144

申请日：2020-03-27

Applicant: Analog Devices, Inc.

Inventor： Devrim Aksin ,  Omid Foroudi

IPC: G05F3/26 ,  H03F3/30 ,  H03F3/45

Abstract: An example current mirror arrangement includes a current mirror circuit, configured to receive an input current signal at an input transistor Q1 and output a mirrored signal at an output transistor Q2. The arrangement further includes a buffer amplifier circuit, having an input coupled to Q1 and an output coupled to Q2. The offset of the buffer amplifier circuit can be adjusted by including circuitry for an input or an output side offset adjustment or by implementing the buffer amplifier circuit as a diamond stage with individually controlled current sources for each of the transistors of the diamond stage. Providing an adjustable offset buffer in a current mirror arrangement may advantageously allow benefiting from the use of a buffer outside of a feedback loop of a current mirror, while being able to reduce the buffer offset due to mismatch between master and slave sides of the current mirror circuit.

公开(公告)号：US11863138B2

公开(公告)日：2024-01-02

申请号：US17959481

申请日：2022-10-04

Applicant: Analog Devices, Inc.

Inventor： Devrim Aksin

IPC: H03F3/45

CPC classification number: H03F3/45179 ,  H03F3/45183 ,  H03F3/45197

Abstract: An example transconductance circuit includes a first portion that includes a first degeneration transistor, configured to receive a first input voltage, and a second portion that includes a second degeneration transistor, coupled to the first degeneration transistor and configured to receive a second input voltage. The first portion further includes a first input transistor, coupled to the first degeneration transistor and configured to provide a first output current, while the second portion further includes a second input transistor, coupled to the second degeneration transistor and configured to provide a second output current. Such a transconductance circuit may be used as an input stage capable of reliably operating within drain-source breakdown voltage of the transistors employed therein even in absence of any other protection devices, and may be significantly faster, consume lower power, and occupy smaller die area compared to conventional transconductance circuits.

公开(公告)号：US11496103B2

公开(公告)日：2022-11-08

申请号：US17026257

申请日：2020-09-20

Applicant: Analog Devices, Inc.

Inventor： Devrim Aksin

IPC: H03F3/45

Abstract: An example transconductance circuit includes a first portion that includes a first degeneration transistor, configured to receive a first input voltage, and a second portion that includes a second degeneration transistor, coupled to the first degeneration transistor and configured to receive a second input voltage. The first portion further includes a first input transistor, coupled to the first degeneration transistor and configured to provide a first output current, while the second portion further includes a second input transistor, coupled to the second degeneration transistor and configured to provide a second output current. Such a transconductance circuit may be used as an input stage capable of reliably operating within drain-source breakdown voltage of the transistors employed therein even in absence of any other protection devices, and may be significantly faster, consume lower power, and occupy smaller die area compared to conventional transconductance circuits.