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公开(公告)号：US08791758B1
公开(公告)日：2014-07-29
申请号：US13784400
申请日：2013-03-04
Applicant: Analog Devices, Inc.
Inventor： Omid Foroudi
IPC: H03F3/45
CPC classification number: H03G3/3036 , H03F1/3211 , H03F3/19 , H03F3/45 , H03F3/4508 , H03F2200/451 , H03F2203/45722
Abstract: Apparatus and methods for buffer linearization are provided. In certain implementations, an amplifier includes a buffer circuit and a gain circuit. The buffer circuit includes a buffer transistor pair used to buffer a differential input signal to generate a differential buffered signal. Additionally, the gain circuit includes a gain transistor pair configured to amplify the buffered differential signal to generate an amplified differential signal. The buffer circuit can include a linearization transistor pair configured to decrease the buffer circuit's output impedance and to provide feedback that reduces changes in the voltage of the differential buffered signal in response to displacement currents associated with the CJC or CGD capacitances of the gain transistor pair.
Abstract translation: 提供缓冲线性化的装置和方法。 在某些实现中，放大器包括缓冲电路和增益电路。 缓冲电路包括用于缓冲差分输入信号以产生差分缓冲信号的缓冲晶体管对。 此外，增益电路包括增益晶体管对，其配置为放大经缓冲的差分信号以产生放大的差分信号。 缓冲电路可以包括线性化晶体管对，其被配置为减小缓冲电路的输出阻抗并提供响应于与增益晶体管对的CJC或CGD电容相关联的位移电流来减小差分缓冲信号的电压变化的反馈。
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公开(公告)号：US10895887B1
公开(公告)日：2021-01-19
申请号：US16724212
申请日：2019-12-21
Applicant: Analog Devices, Inc.
Inventor： Devrim Aksin , Omid Foroudi
Abstract: An example current mirror arrangement includes a first portion and a second portion, each of which includes a current mirror having transistors Q1 and Q2, a buffer amplifier that has an input coupled to a base/gate terminal of Q1 and an output coupled to a base/gate terminal of Q2, a master resistor coupled to an emitter/source terminal of Q1, and a slave resistor coupled to an emitter/source terminal of Q2. Furthermore, the slave resistor of the first portion is coupled to the slave resistor of the second portion. Providing additional resistors on master and slave sides of a current mirror arrangement may advantageously allow benefiting from the use of buffers outside of a feedback loop of a current mirror while reducing the sensitivity of the current mirror arrangement to buffer offsets.
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公开(公告)号：US11262782B2
公开(公告)日：2022-03-01
申请号：US16861915
申请日：2020-04-29
Applicant: Analog Devices, Inc.
Inventor： Devrim Aksin , Omid Foroudi
Abstract: An example current mirror arrangement includes a current mirror circuit, configured to receive an input current signal at an input transistor Q1 and output a mirrored signal at an output transistor Q2. The arrangement further includes a semi-cascoding circuit that includes transistors Q3, Q4, and a two-terminal passive network. The transistor Q3 is coupled to, and forms a cascode with, the output transistor Q2. The transistor Q4 is coupled to the transistor Q3. The base/gate of the transistor Q3 is coupled to a bias voltage Vref, and the base/gate of the transistor Q4 is coupled to a bias voltage Vref1 via the two-terminal passive network. Nonlinearity of the output current from such a current mirror arrangement may be reduced by selecting appropriate impedance of the two-terminal passive network and selecting appropriate bias voltages Vref and Vref1.
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公开(公告)号：US10374602B1
公开(公告)日：2019-08-06
申请号：US15878280
申请日：2018-01-23
Applicant: Analog Devices, Inc.
Inventor： Omid Foroudi
IPC: H03K17/687
Abstract: Techniques for linearizing a field effect transistor (FET) are provided. In an example, a method can include averaging a voltage at a drain node of the FET and a voltage at a source node of the FET to provide an average voltage, and applying the average voltage to a gate node of the FET.
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Patent Agency Ranking
公开(公告)号：US11106233B1
公开(公告)日：2021-08-31
申请号：US16774283
申请日：2020-01-28
Applicant: Analog Devices, Inc.
Inventor： Devrim Aksin , Omid Foroudi
Abstract: An example current mirror arrangement includes a current mirror circuit having an input transistor and an output transistor, where the base/gate terminal of the input transistor is coupled to its collector/drain terminal via a transistor matrix that includes a plurality of transistors. Transistors of the transistor matrix, together with the input transistor, form two parallel feedback loops, such that the input transistor is part of both loops. The first loop is a fast, low-gain loop, while the second loop is a slow, high-gain loop. At lower input frequencies, the high-gain loop may properly bias and accurately generate voltage at the base/gate terminal of the input transistor, while at higher input frequencies the fast loop may significantly extend the linear operating frequency band. Consequently, a current mirror arrangement with improvements in terms of linearity and signal bandwidth may be realized.
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公开(公告)号：US20190229725A1
公开(公告)日：2019-07-25
申请号：US15878280
申请日：2018-01-23
Applicant: Analog Devices, Inc.
Inventor： Omid Foroudi
IPC: H03K17/687
CPC classification number: H03K17/687 , H03K2217/0054
Abstract: Techniques for linearizing a field effect transistor (FET) are provided. In an example, a method can include averaging a voltage at a drain node of the FET and a voltage at a source node of the FET to provide an average voltage, and applying the average voltage to a gate node of the FET.
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公开(公告)号：US11188112B2
公开(公告)日：2021-11-30
申请号：US16832144
申请日：2020-03-27
Applicant: Analog Devices, Inc.
Inventor： Devrim Aksin , Omid Foroudi
Abstract: An example current mirror arrangement includes a current mirror circuit, configured to receive an input current signal at an input transistor Q1 and output a mirrored signal at an output transistor Q2. The arrangement further includes a buffer amplifier circuit, having an input coupled to Q1 and an output coupled to Q2. The offset of the buffer amplifier circuit can be adjusted by including circuitry for an input or an output side offset adjustment or by implementing the buffer amplifier circuit as a diamond stage with individually controlled current sources for each of the transistors of the diamond stage. Providing an adjustable offset buffer in a current mirror arrangement may advantageously allow benefiting from the use of a buffer outside of a feedback loop of a current mirror, while being able to reduce the buffer offset due to mismatch between master and slave sides of the current mirror circuit.
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公开(公告)号：US09048801B2
公开(公告)日：2015-06-02
申请号：US14337944
申请日：2014-07-22
Applicant: Analog Devices, Inc.
Inventor： Omid Foroudi
CPC classification number: H03G3/3036 , H03F1/3211 , H03F3/19 , H03F3/45 , H03F3/4508 , H03F2200/451 , H03F2203/45722
Abstract: Apparatus and methods for buffer linearization are provided. In certain implementations, an amplifier includes a buffer circuit and a gain circuit. The buffer circuit includes a buffer transistor pair used to buffer a differential input signal to generate a differential buffered signal. Additionally, the gain circuit includes a gain transistor pair configured to amplify the buffered differential signal to generate an amplified differential signal. The buffer circuit can include a linearization transistor pair configured to decrease the buffer circuit's output impedance and to provide feedback that reduces changes in the voltage of the differential buffered signal in response to displacement currents associated with the CJC or CGD capacitances of the gain transistor pair.
Abstract translation: 提供缓冲线性化的装置和方法。 在某些实现中，放大器包括缓冲电路和增益电路。 缓冲电路包括用于缓冲差分输入信号以产生差分缓冲信号的缓冲晶体管对。 此外，增益电路包括增益晶体管对，其配置为放大经缓冲的差分信号以产生放大的差分信号。 缓冲电路可以包括线性化晶体管对，其被配置为减小缓冲电路的输出阻抗并提供响应于与增益晶体管对的CJC或CGD电容相关联的位移电流来减小差分缓冲信号的电压变化的反馈。
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公开(公告)号：US20140333381A1
公开(公告)日：2014-11-13
申请号：US14337944
申请日：2014-07-22
Applicant: Analog Devices, Inc.
Inventor： Omid Foroudi
CPC classification number: H03G3/3036 , H03F1/3211 , H03F3/19 , H03F3/45 , H03F3/4508 , H03F2200/451 , H03F2203/45722
Abstract: Apparatus and methods for buffer linearization are provided. In certain implementations, an amplifier includes a buffer circuit and a gain circuit. The buffer circuit includes a buffer transistor pair used to buffer a differential input signal to generate a differential buffered signal. Additionally, the gain circuit includes a gain transistor pair configured to amplify the buffered differential signal to generate an amplified differential signal. The buffer circuit can include a linearization transistor pair configured to decrease the buffer circuit's output impedance and to provide feedback that reduces changes in the voltage of the differential buffered signal in response to displacement currents associated with the CJC or CGD capacitances of the gain transistor pair.
Abstract translation: 提供缓冲线性化的装置和方法。 在某些实现中，放大器包括缓冲电路和增益电路。 缓冲电路包括用于缓冲差分输入信号以产生差分缓冲信号的缓冲晶体管对。 此外，增益电路包括增益晶体管对，其配置为放大经缓冲的差分信号以产生放大的差分信号。 缓冲电路可以包括线性化晶体管对，其被配置为减小缓冲电路的输出阻抗并提供响应于与增益晶体管对的CJC或CGD电容相关联的位移电流来减小差分缓冲信号的电压变化的反馈。
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