公开(公告)号：US09813056B2

公开(公告)日：2017-11-07

申请号：US14885601

申请日：2015-10-16

Applicant: Analog Devices Global

Inventor： Bin Shao ,  Danzhu Lu ,  Junxiao Chen

IPC: H03K17/10 ,  H03K17/06 ,  H03K17/687 ,  H03K17/22

CPC classification number: H03K17/6871 ,  H03K17/223

Abstract: An active voltage divider circuit is provided comprising: a first node; a second node; a third node; multiple FET load devices coupled in series between the first node and the second node; multiple first switches, each associated with a different FET load device and configured to selectably couple a respective associated bypass circuit between source and drain of its associated FET load device; and second switch circuitry configured to selectably couple a drain of a FET load device, from among the multiple FET load devices, to the third node.

公开(公告)号：US20170085263A1

公开(公告)日：2017-03-23

申请号：US14885601

申请日：2015-10-16

Applicant: Analog Devices Global

Inventor： Bin Shao ,  Danzhu Lu ,  Junxiao Chen

IPC: H03K17/687

CPC classification number: H03K17/6871 ,  H03K17/223

Abstract: An active voltage divider circuit is provided comprising: a first node; a second node; a third node; multiple FET load devices coupled in series between the first node and the second node; multiple first switches, each associated with a different FET load device and configured to selectably couple a respective associated bypass circuit between source and drain of its associated FET load device; and second switch circuitry configured to selectably couple a drain of a FET load device, from among the multiple FET load devices, to the third node.