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公开(公告)号：US10599171B2
公开(公告)日：2020-03-24
申请号：US16050742
申请日：2018-07-31
Applicant: Analog Devices Global Unlimited Company
Inventor： Langyuan Wang , Danzhu Lu , Xiaohan Gong , Bin Shao
Abstract: An electronic circuit includes parallel linear regulator circuits that support a range of different load currents. The electronic circuit includes a first linear regulator circuit coupled to an output node, a second linear regulator circuit coupled in parallel with the first linear regulator circuit and the output node, and a control circuit. The control circuit is configured to monitor the output node and to suppress or inhibit the second linear regulator circuit from supplying the output node when a representation of load power consumption is below a specified threshold. The first linear regulator circuit is configured to continue to supply a portion of the load power when the representation of load power consumption is above the specified threshold, and the control circuit may disable the second linear regulator circuit when the representation of load power consumption is below the specified threshold.
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公开(公告)号：US20200042026A1
公开(公告)日：2020-02-06
申请号：US16050742
申请日：2018-07-31
Applicant: Analog Devices Global Unlimited Company
Inventor： Langyuan Wang , Danzhu Lu , Xiaohan Gong , Bin Shao
Abstract: An electronic circuit includes parallel linear regulator circuits that support a range of different load currents. The electronic circuit includes a first linear regulator circuit coupled to an output node, a second linear regulator circuit coupled in parallel with the first linear regulator circuit and the output node, and a control circuit. The control circuit is configured to monitor the output node and to suppress or inhibit the second linear regulator circuit from supplying the output node when a representation of load power consumption is below a specified threshold. The first linear regulator circuit is configured to continue to supply a portion of the load power when the representation of load power consumption is above the specified threshold, and the control circuit may disable the second linear regulator circuit when the representation of load power consumption is below the specified threshold.
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公开(公告)号：US10305369B2
公开(公告)日：2019-05-28
申请号：US15443950
申请日：2017-02-27
Applicant: Analog Devices Global
Inventor： Bin Shao , Sean Kowalik , Alan S. Walsh , Danzhu Lu
IPC: H02M1/12 , G01S7/48 , H02M3/158 , H02M1/14 , H02M3/335 , G01S7/484 , G01S7/486 , H01S5/042 , H02M1/08 , H03M1/80
Abstract: This application discusses techniques for reducing the energy of an output ripple in a voltage converter at a switching frequency of the voltage converter. In certain examples, an amplitude of a reference voltage can be modulated with a time-varying random value or pseudo-random value to provide a reduction in the energy of the output ripple at the switching frequency of the voltage converter.
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公开(公告)号：US09391519B2
公开(公告)日：2016-07-12
申请号：US14311907
申请日：2014-06-23
Applicant: Analog Devices Global
Inventor： Danzhu Lu , Xiaohan Gong , Bin Shao
IPC: H03K3/356 , H02M3/158 , H03K19/017
CPC classification number: H02M3/158 , H03K3/356 , H03K19/01721
Abstract: A device to detect an electrical signal is provided. The device includes sensing, output, and pull-down nodes. The device includes a pull-down circuit having a native metal-oxide-semiconductor field-effect transistor (MOSFET) to pull down the output node to approximately a voltage of the pull-down node. The device includes a switch circuit having a junction field-effect transistor (JFET). The JFET turns on the pull-down circuit in response to a voltage of the sensing node being less than a first threshold. The JFET also turns off the pull-down circuit in response to the voltage of the sensing node being greater than the first threshold.
Abstract translation: 提供了一种用于检测电信号的装置。 该设备包括感测，输出和下拉节点。 该器件包括具有天然金属氧化物半导体场效应晶体管（MOSFET）的下拉电路，以将输出节点下拉到大约下拉节点的电压。 该器件包括具有结型场效应晶体管（JFET）的开关电路。 JFET响应于感测节点的电压小于第一阈值而导通下拉电路。 JFET还响应于感测节点的电压大于第一阈值而关断下拉电路。
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公开(公告)号：US20150349637A1
公开(公告)日：2015-12-03
申请号：US14311907
申请日：2014-06-23
Applicant: Analog Devices Global
Inventor： Danzhu Lu , Xiaohan Gong , Bin Shao
IPC: H02M3/158
CPC classification number: H02M3/158 , H03K3/356 , H03K19/01721
Abstract: A device to detect an electrical signal is provided. The device includes sensing, output, and pull-down nodes. The device includes a pull-down circuit having a native metal-oxide-semiconductor field-effect transistor (MOSFET) to pull down the output node to approximately a voltage of the pull-down node. The device includes a switch circuit having a junction field-effect transistor (JFET). The JFET turns on the pull-down circuit in response to a voltage of the sensing node being less than a first threshold. The JFET also turns off the pull-down circuit in response to the voltage of the sensing node being greater than the first threshold.
Abstract translation: 提供了一种用于检测电信号的装置。 该设备包括感测，输出和下拉节点。 该器件包括具有天然金属氧化物半导体场效应晶体管（MOSFET）的下拉电路，以将输出节点下拉到大约下拉节点的电压。 该器件包括具有结型场效应晶体管（JFET）的开关电路。 JFET响应于感测节点的电压小于第一阈值而导通下拉电路。 JFET还响应于感测节点的电压大于第一阈值而关断下拉电路。
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Patent Agency Ranking
公开(公告)号：US20180226878A1
公开(公告)日：2018-08-09
申请号：US15443950
申请日：2017-02-27
Applicant: Analog Devices Global
Inventor： Bin Shao , Sean Kowalik , Alan S. Walsh , Danzhu Lu
IPC: H02M1/12
CPC classification number: H02M1/12 , G01S7/484 , G01S7/4865 , H01S5/0428 , H02M1/08 , H02M1/143 , H02M3/158 , H02M3/33507 , H03M1/808
Abstract: This application discusses techniques for reducing the energy of an output ripple in a voltage converter at a switching frequency of the voltage converter. In certain examples, an amplitude of a reference voltage can be modulated with a time-varying random value or pseudo-random value to provide a reduction in the energy of the output ripple at the switching frequency of the voltage converter.
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公开(公告)号：US20170085263A1
公开(公告)日：2017-03-23
申请号：US14885601
申请日：2015-10-16
Applicant: Analog Devices Global
Inventor： Bin Shao , Danzhu Lu , Junxiao Chen
IPC: H03K17/687
CPC classification number: H03K17/6871 , H03K17/223
Abstract: An active voltage divider circuit is provided comprising: a first node; a second node; a third node; multiple FET load devices coupled in series between the first node and the second node; multiple first switches, each associated with a different FET load device and configured to selectably couple a respective associated bypass circuit between source and drain of its associated FET load device; and second switch circuitry configured to selectably couple a drain of a FET load device, from among the multiple FET load devices, to the third node.
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公开(公告)号：US10224800B2
公开(公告)日：2019-03-05
申请号：US15618270
申请日：2017-06-09
Applicant: Analog Devices Global
Abstract: Techniques for indicating a load level of a DC-DC switching converter are provided. IN an example, a method for real-time load current detection for a switching converter using a discontinuous conduction mode (DCM) of operation can include generating a minimum DCM current threshold based on an reference current source and a duty cycle of the switching converter, receiving a representation of inductor charge current from power switch of the switching converter at a comparator, comparing the representation to the DCM current threshold, and controlling the power switch using a discontinuous conduction mode of the switching converter when a peak of the representation exceeds the minimum DCM current threshold.
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公开(公告)号：US20180358884A1
公开(公告)日：2018-12-13
申请号：US15618270
申请日：2017-06-09
Applicant: Analog Devices Global
CPC classification number: H02M1/08 , H02M3/156 , H02M2001/0009
Abstract: Techniques for indicating a load level of a DC-DC switching converter are provided. IN an example, a method for real-time load current detection for a switching converter using a discontinuous conduction mode (DCM) of operation can include generating a minimum DCM current threshold based on an reference current source and a duty cycle of the switching converter, receiving a representation of inductor charge current from power switch of the switching converter at a comparator, comparing the representation to the DCM current threshold, and controlling the power switch using a discontinuous conduction mode of the switching converter when a peak of the representation exceeds the minimum DCM current threshold.
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公开(公告)号：US09813056B2
公开(公告)日：2017-11-07
申请号：US14885601
申请日：2015-10-16
Applicant: Analog Devices Global
Inventor： Bin Shao , Danzhu Lu , Junxiao Chen
IPC: H03K17/10 , H03K17/06 , H03K17/687 , H03K17/22
CPC classification number: H03K17/6871 , H03K17/223
Abstract: An active voltage divider circuit is provided comprising: a first node; a second node; a third node; multiple FET load devices coupled in series between the first node and the second node; multiple first switches, each associated with a different FET load device and configured to selectably couple a respective associated bypass circuit between source and drain of its associated FET load device; and second switch circuitry configured to selectably couple a drain of a FET load device, from among the multiple FET load devices, to the third node.
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