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1.发明申请公开(公告)号：US20240405518A1
公开(公告)日：2024-12-05
申请号：US18679352
申请日：2024-05-30
Inventor： David J. Clarke , Alan J. O'Donnell , Shaun Bradley , Stephen Denis Heffernan , Patrick Martin McGuinness , Padraig L. Fitzgerald , Edward John Coyne , Michael P. Lynch , John Anthony Cleary , John Ross Wallrabenstein , Paul Joseph Maher , Andrew Christopher Linehan , Gavin Patrick Cosgrave , Michael James Twohig , Jan Kubik , Jochen Schmitt , David Aherne , Mary McSherry , Anne M. McMahon , Stanislav Jolondcovschi , Cillian Burke
IPC: H01T4/10
Abstract: Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a spark gap device includes first and second conductive layers formed over a substrate, where the first and second conductive layers are electrically connected to first and second voltage nodes, respectively. The first conductive layer includes a plurality of arcing tips configured to form arcing electrode pairs with the second conductive layer to form an arc discharge in response to an EOS voltage between the first and second voltage nodes. The spark gap device further includes a series ballast resistor electrically connected between the arcing tips and the first voltage node, where the ballast resistor in formed in a metallization layer over the substrate and a resistance of the series ballast resistor is substantially higher than a resistance of the second conductive layer.
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Patent Agency Ranking
公开(公告)号：US11984479B2
公开(公告)日：2024-05-14
申请号：US17177556
申请日：2021-02-17
Inventor： Dennis A. Dempsey , Andrew Christopher Linehan , Seamus P. Whiston , David J. Rohan
CPC classification number: H01L29/1041 , H01L29/0649 , H01L29/66537
Abstract: The present disclosure relates to a field effect transistor (FET) structure. The FET structure has a substrate, an active region, a dielectric layer provided over a channel of the active region and a gate provided over the dielectric layer. The active region comprises a source, a drain and the channel provided between the source and the drain. The active region is surrounded by an isolation trench, such that width edges of the channel are directly adjacent to the isolation trench. Current paths run between the source and the drain, through the channel. The FET is configured such that current paths running proximal to the channel edges are reduced or weaker in comparison to a dominant current path running through a center of the channel. One or more of the channel, the dielectric layer or the substrate can be modified or adapted to provide the reduced and dominant current paths. In one example, the center of the channel away from the edges has a first doping concentration of a first conductivity type, and the sides of the channel along the channel edges have a second doping concentration of the first conductivity type, where the second doping concentration is greater than the first doping concentration. In another example, the dielectric layer is thicker over the sides of the channel and thinner over the center of the channel. In another example, regions of the substrate below the sides of the channel have a higher doping concentration than a region of the substrate below the center of the channel. In some examples, the FET structure has both the dielectric layer of different thicknesses and the different doping concentrations in the channel and/or the substrate.
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公开(公告)号：US20240405517A1
公开(公告)日：2024-12-05
申请号：US18679348
申请日：2024-05-30
Inventor： David J. Clarke , Alan J. O'Donnell , Shaun Bradley , Stephen Denis Heffernan , Patrick Martin McGuinness , Padraig L. Fitzgerald , Edward John Coyne , Michael P. Lynch , John Anthony Cleary , John Ross Wallrabenstein , Paul Joseph Maher , Andrew Christopher Linehan , Gavin Patrick Cosgrave , Michael James Twohig , Jan Kubik , Jochen Schmitt , David Aherne , Mary McSherry , Anne M. McMahon , Stanislav Jolondcovschi , Cillian Burke
Abstract: Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a spark gap array includes a sheet resistor and an array of arcing electrode pairs formed over a substrate. The array of arcing electrode pairs includes first arcing electrodes formed on the sheet resistor and a second arcing electrode arranged as a sheet formed over the first arcing electrodes and separated from the first arcing electrodes by an arcing gap. The first arcing electrodes and second arcing electrode are electrically connected to first and second voltage nodes, respectively, and the arcing electrode pairs are configured to generate arc discharges in response to an EOS voltage signal received between the first and second voltage nodes.
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4.发明申请公开(公告)号：US20250030237A1
公开(公告)日：2025-01-23
申请号：US18679379
申请日：2024-05-30
Inventor： David J. Clarke , Alan J. O'Donnell , Shaun Stephen Bradley , Stephen Denis Heffernan , Patrick Martin McGuinness , Padraig L. Fitzgerald , Edward John Coyne , Michael P. Lynch , John Anthony Cleary , John Ross Wallrabenstein , Paul Joseph Maher , Andrew Christopher Linehan , Gavin Patrick Cosgrave , Michael James Twohig , Jan Kubik , Jochen Schmitt , David Aherne , Mary McSherry , Anne M. McMahon , Stanislav Jolondcovschi , Cillian Burke
Abstract: Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a vertical spark gap device includes a substrate having a horizontal main surface and a plurality of pairs of conductive layers over the horizontal main surface. Different ones of the pairs are separated by different vertical distances such that each pair serves as an arcing electrode pair and different ones of the arcing electrode pairs are configured to arc discharge at different voltages.
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公开(公告)号：US20240405519A1
公开(公告)日：2024-12-05
申请号：US18679364
申请日：2024-05-30
Inventor： David J. Clarke , Alan J. O'Donnell , Shaun Bradley , Stephen Denis Heffernan , Patrick Martin McGuinness , Padraig L. Fitzgerald , Edward John Coyne , Michael P. Lynch , John Anthony Cleary , John Ross Wallrabenstein , Paul Joseph Maher , Andrew Christopher Linehan , Gavin Patrick Cosgrave , Michael James Twohig , Jan Kubik , Jochen Schmitt , David Aherne , Mary McSherry , Anne M. McMahon , Stanislav Jolondcovschi , Cillian Burke
Abstract: Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a vertical spark gap device includes a substrate having a horizontal main surface, a first conductive layer and a second conductive layer each extending over the substrate and substantially parallel to the horizontal main surface while being separated in a vertical direction crossing the horizontal main surface. One of the first and second conductive layers is electrically connected to a first voltage node and the other of the first and second conductive layers is electrically connected to a second voltage node. The first and second conductive layers serve as one or more arcing electrode pairs and have overlapping portions configured to generate one or more arc discharges extending generally in the vertical direction in response to an EOS voltage signal received between the first and second voltage nodes.
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公开(公告)号：US20220262904A1
公开(公告)日：2022-08-18
申请号：US17177556
申请日：2021-02-17
Inventor： Dennis A. Dempsey , Andrew Christopher Linehan , Seamus P. Whiston , David J. Rohan
Abstract: The present disclosure relates to a field effect transistor (FET) structure. The FET structure has a substrate, an active region, a dielectric layer provided over a channel of the active region and a gate provided over the dielectric layer. The active region comprises a source, a drain and the channel provided between the source and the drain. The active region is surrounded by an isolation trench, such that width edges of the channel are directly adjacent to the isolation trench. Current paths run between the source and the drain, through the channel. The FET is configured such that current paths running proximal to the channel edges are reduced or weaker in comparison to a dominant current path running through a center of the channel. One or more of the channel, the dielectric layer or the substrate can be modified or adapted to provide the reduced and dominant current paths. In one example, the center of the channel away from the edges has a first doping concentration of a first conductivity type, and the sides of the channel along the channel edges have a second doping concentration of the first conductivity type, where the second doping concentration is greater than the first doping concentration. In another example, the dielectric layer is thicker over the sides of the channel and thinner over the center of the channel. In another example, regions of the substrate below the sides of the channel have a higher doping concentration than a region of the substrate below the center of the channel. In some examples, the FET structure has both the dielectric layer of different thicknesses and the different doping concentrations in the channel and/or the substrate.
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