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1.发明授权公开(公告)号：US11563442B2
公开(公告)日：2023-01-24
申请号：US17389428
申请日：2021-07-30
Inventor： Victor Kozlov , Sharvil Pradeep Patil , Hajime Shibata
Abstract: Calibration of continuous-time (CT) residue generation systems can account and compensate for mismatches in magnitude and phase that may be caused by fabrication processes, temperature, and voltage variations. In particular, calibration may be performed by providing one or more known test signals as an input to a CT residue generation system, analyzing the output of the system corresponding to the known input, and then adjusting one or more parameters of a forward and/or a feedforward path of the system so that the difference in transfer functions of these paths may be reduced/minimized. Calibrating CT residue generation systems using test signals may help decrease the magnitude of the residue signals generated by such systems, and, consequently, advantageously increase an error correction range of such systems or of further stages that may use the residue signals as input.
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Patent Agency Ranking
公开(公告)号：US20240364356A1
公开(公告)日：2024-10-31
申请号：US18139779
申请日：2023-04-26
Inventor： Asha Ganesan , Donald W. Paterson , Sharvil Pradeep Patil , Nevena Rakuljic
CPC classification number: H03M1/50 , H03M1/1009 , H03M1/201 , H03M1/662
Abstract: CT ADCs based on continuous-time residue generation systems require accurate estimation of analog transfer functions. This is done by using a pseudo random bit sequence, injected using a DAC, that traverses the transfer function to be measured. Mismatch in the injection DAC introduces errors in the transfer function estimation and results in poor NSD at the ADC output. Techniques are described to improve the accuracy of the transfer function estimate despite DAC mismatch and despite the presence of an input signal.
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公开(公告)号：US12107590B2
公开(公告)日：2024-10-01
申请号：US18049278
申请日：2022-10-24
Inventor： Sharvil Pradeep Patil , Asha Ganesan , Hajime Shibata , Donald W. Paterson , Haiyang Zhu
CPC classification number: H03M1/0604 , H03M1/1038 , H03M1/1047 , H03M1/164
Abstract: Continuous-time (CT) analog-to-digital converters (ADCs) implementing digital correction of digital-to-analog converter (DAC) errors are disclosed. In a CT pipeline stage of a CT ADC, a CT analog input signal is sent to two different paths. A first path (a “feedforward” path) includes a cascade of a sub-ADC and a sub-DAC. A second path (a “forward” path) includes an analog delay circuit to align the delays of the input signal in the feedforward and forward paths. A combiner subtracts the output of the analog delay of the forward path from the output of the sub-DAC in the feedforward path to generate a residue signal. Devices and methods disclosed herein are based on recognition that, if the errors introduced by the sub-DAC are known, they can be corrected in the digital domain during reconstruction, achieving superior NSD and distortion performance compared to conventional approaches.
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公开(公告)号：US11652491B2
公开(公告)日：2023-05-16
申请号：US17390852
申请日：2021-07-30
Inventor： Victor Kozlov , Donald W. Paterson , Sharvil Pradeep Patil , Hajime Shibata
CPC classification number: H03M1/0641
Abstract: Mechanisms for reducing or eliminating a quantization error caused by a quantizer of a continuous-time (CT) residue generation system are disclosed. In particular, systems and methods described herein are based on using a dither generation and injection circuit that can perform a high-pass filtering of the additive dither signal (i.e., a high-pass shaped dither signal). Using high-pass shaped dither signals is expected to improve quantizer linearity without significantly reducing the available error correction range. The applied dither may be particularly effective at minimizing signal-dependent distortion in ADC output spectrum caused by the quantizer when the quantization error cancellation accuracy may be insufficient.
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公开(公告)号：US11218158B1
公开(公告)日：2022-01-04
申请号：US17154138
申请日：2021-01-21
Inventor： Sharvil Pradeep Patil , Donald W. Paterson , Prawal Man Shrestha , Asha Ganesan , Yue Yin , Zhao Li , Victor Kozlov , Hajime Shibata
Abstract: In one aspect, a transfer function (TF) estimation circuit configured to generate an estimate of a TF undergone by signals between an input of a digital-to-analog converter (DAC) of a feedforward path of a continuous-time (CT) stage of an analog-to-digital converter (ADC) and an output of a backend ADC of the ADC is disclosed. The TF estimation circuit includes one or more circuits configured to generate a first cross-correlation output by cross-correlating digital versions of signals based on a test signal provided to the CT stage and an output signal of the backend ADC, generate a second cross-correlation output by cross-correlating digital versions of signals based on the test signal and an output signal of a quantizer of the feedforward path of the CT stage, and generate the estimate of the TF based on the first and second cross-correlation outputs.
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公开(公告)号：US11133814B1
公开(公告)日：2021-09-28
申请号：US17110902
申请日：2020-12-03
Inventor： Sharvil Pradeep Patil , Kimo Tam , Hajime Shibata
Abstract: An example residue generation arrangement for a continuous time or hybrid ADC includes a delay circuit having a cascade of analog delay sections, each section to provide a respective delay to an analog input signal, thus providing a delayed analog input signal at the output of the delay circuit. The delay circuit further includes a selector, configured to select an input or an output of one of the delay sections to provide as an input signal to a quantizer of a feedforward path. The quantizer may generate a digital input to a DAC of the feedforward path based on the output of the selector, and the DAC may generate a feedforward path analog output based on the digital signal generated by the quantizer. The arrangement further includes a summation node, configured to generate a residue signal based on the delayed analog input and the feedforward path analog output.
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