公开(公告)号：US09048847B2

公开(公告)日：2015-06-02

申请号：US14034917

申请日：2013-09-24

Applicant: Analog Devices Technology

Inventor： David J McLaurin ,  Christopher W Angell ,  Michael F Keaveney

IPC: H03L7/00 ,  H03L7/085 ,  H03L7/10

CPC classification number: H03L7/1976 ,  H03L7/085 ,  H03L7/104 ,  H03L7/199 ,  H03L7/23

Abstract: Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.

Abstract translation: 提供了用于同步锁相环（PLL）的装置和方法。 在某些实现中，分数N合成器包括PLL和控制PLL的分频值的控制电路。 控制电路包括内插器，复位相位调整计算器和同步电路。 内插器可以控制PLL分频值的小数部分。 复位相位调整计算器可以包括一个计数器，用于对分数N合成器的初始化后的参考时钟信号的周期数进行计数，并且复位相位调整计算器可以基于计数产生相位调整信号。 同步电路可以响应于同步信号来同步PLL，并且可以校正由相位调整信号指示的同步相位误差。