公开(公告)号：US08423929B2

公开(公告)日：2013-04-16

申请号：US12906857

申请日：2010-10-18

申请人： Anand Pandurangan ,  Pius Ng ,  Siva Selvaraj ,  Sanjay Banerjee ,  Ananth Durbha ,  Suresh Kadiyala ,  Satish Padmanabhan

发明人： Anand Pandurangan ,  Pius Ng ,  Siva Selvaraj ,  Sanjay Banerjee ,  Ananth Durbha ,  Suresh Kadiyala ,  Satish Padmanabhan

IPC分类号： G06F17/50

CPC分类号： G06F15/76 ,  G06F17/505 ,  G06F2217/68

摘要： Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了系统和方法以自动生成由计算机可读代码描述的定制集成电路（IC）的处理器架构。 IC具有一个或多个时序和硬件限制。 该系统从静态简档和计算机可读代码的动态简档中提取定义处理器架构的参数; 通过改变一个或多个参数来迭代地优化处理器架构，直到满足表示为成本函数的所有定时和硬件约束为止; 并将生成的处理器架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

公开(公告)号：US20120096420A1

公开(公告)日：2012-04-19

申请号：US12906857

申请日：2010-10-18

申请人： Anand Pandurangan ,  Pius Ng ,  Siva Selvaraj ,  Sanjay Banerjee ,  Ananth Durbha ,  Suresh Kadiyala ,  Satish Padmanabhan

发明人： Anand Pandurangan ,  Pius Ng ,  Siva Selvaraj ,  Sanjay Banerjee ,  Ananth Durbha ,  Suresh Kadiyala ,  Satish Padmanabhan

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F15/76 ,  G06F17/505 ,  G06F2217/68

摘要： Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了系统和方法以自动生成由计算机可读代码描述的定制集成电路（IC）的处理器架构。 IC具有一个或多个时序和硬件限制。 该系统从静态简档和计算机可读代码的动态简档中提取定义处理器架构的参数; 通过改变一个或多个参数来迭代地优化处理器架构，直到满足表示为成本函数的所有定时和硬件约束为止; 并将生成的处理器架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

公开(公告)号：US08589854B2

公开(公告)日：2013-11-19

申请号：US12835628

申请日：2010-07-13

申请人： Pius Ng ,  Satish Padmanabhan ,  Anand Pandurangan ,  Ananth Durbha ,  Suresh Kadiyala ,  Gary Oblock

发明人： Pius Ng ,  Satish Padmanabhan ,  Anand Pandurangan ,  Ananth Durbha ,  Suresh Kadiyala ,  Gary Oblock

IPC分类号： G06F11/22

CPC分类号： G06F17/505 ,  G06F2217/78

摘要： Systems and methods are disclosed to manage power in a custom integrated circuit (IC) design by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks and one or more power domains; determining when each processing block is needed based on the code profile and assigning each block to one of the power domains; and gating the power domains with power based on the code profile; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了通过接收包括计算机可读代码的定制集成电路的规范并生成计算机可读代码的简档以确定指令使用的方式来管理定制集成电路（IC）设计中的电力的系统和方法; 自动生成针对所述计算机可读代码唯一定制的处理器架构，所述处理器架构具有一个或多个处理块和一个或多个电源域; 基于所述代码简档来确定每个处理块是否需要;以及将每个块分配给所述功率域中的一个; 并根据代码简档对功率域进行选通; 以及将生成的架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

公开(公告)号：US20130263067A1

公开(公告)日：2013-10-03

申请号：US13626878

申请日：2012-09-25

申请人： Satish Padmanabhan ,  Pius Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

发明人： Satish Padmanabhan ,  Pius Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5022 ,  G06F17/5045

摘要： Systems and methods are disclosed to automatically design a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture with programmable processor and one or more co-processors for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了通过接收定制集成电路的规范来自动设计定制集成电路的系统和方法，包括计算机可读代码和定制集成电路上的一个或多个约束; 自动生成具有可编程处理器的计算机体系结构和用于最适合约束的计算机可读代码的一个或多个协处理器; 基于代码简档自动确定指令执行序列，并重新分配或延迟指令序列以在一个或多个处理块上扩展操作以减少热点; 为定制集成电路上的计算机可读代码自动生成相关的测试套件和向量; 并自动合成设计的架构并生成用于半导体制造的定制集成电路的计算机可读描述。

公开(公告)号：US08225247B2

公开(公告)日：2012-07-17

申请号：US12835603

申请日：2010-07-13

申请人： Satish Padmanabhan ,  Pius Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

发明人： Satish Padmanabhan ,  Pius Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5022

摘要： Systems and methods are disclosed to automatically design a custom integrated circuit includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically devising a processor architecture and generating a processor chip specification uniquely customized to the computer readable code which satisfies the constraints; and synthesizing the chip specification into a layout of the custom integrated circuit.

摘要翻译： 公开了系统和方法以自动设计定制集成电路，包括接收定制集成电路的规范，包括计算机可读代码和定制集成电路上的一个或多个约束; 自动设计处理器架构并且生成独特地定制为满足约束的计算机可读代码的处理器芯片规范; 并将芯片规格合成为定制集成电路的布局。

公开(公告)号：US20120017198A1

公开(公告)日：2012-01-19

申请号：US12835628

申请日：2010-07-13

申请人： Pius Ng ,  Satish Padmanabhan ,  Anand Pandurangan ,  Ananth Durbha ,  Suresh Kadiyala ,  Gary Oblock

发明人： Pius Ng ,  Satish Padmanabhan ,  Anand Pandurangan ,  Ananth Durbha ,  Suresh Kadiyala ,  Gary Oblock

IPC分类号： G06F9/44 ,  G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/78

摘要： Systems and methods are disclosed to manage power in a custom integrated circuit (IC) design by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks and one or more power domains; determining when each processing block is needed based on the code profile and assigning each block to one of the power domains; and gating the power domains with power based on the code profile; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了通过接收包括计算机可读代码的定制集成电路的规范并生成计算机可读代码的简档以确定指令使用的方式来管理定制集成电路（IC）设计中的电力的系统和方法; 自动生成针对所述计算机可读代码唯一定制的处理器架构，所述处理器架构具有一个或多个处理块和一个或多个电源域; 基于所述代码简档来确定每个处理块是否需要;以及将每个块分配给所述功率域中的一个; 并根据代码简档对功率域进行选通; 以及将生成的架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

公开(公告)号：US20120017185A1

公开(公告)日：2012-01-19

申请号：US12835603

申请日：2010-07-13

申请人： Satish Padmanabhan ,  Pius Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

发明人： Satish Padmanabhan ,  Pius Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5022

摘要： Systems and methods are disclosed to automatically design a custom integrated circuit includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically devising a processor architecture and generating a processor chip specification uniquely customized to the computer readable code which satisfies the constraints; and synthesizing the chip specification into a layout of the custom integrated circuit.

摘要翻译： 公开了系统和方法以自动设计定制集成电路，包括接收定制集成电路的规范，包括计算机可读代码和定制集成电路上的一个或多个约束; 自动设计处理器架构并且生成独特地定制为满足约束的计算机可读代码的处理器芯片规范; 并将芯片规格合成为定制集成电路的布局。

公开(公告)号：US20120017187A1

公开(公告)日：2012-01-19

申请号：US12835621

申请日：2010-07-13

申请人： Satish Padmanabhan ,  Plus Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

发明人： Satish Padmanabhan ,  Plus Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5022 ,  G06F17/5045

摘要： Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed. The method includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; continuously evaluating and optimizing one or more factors including physical implementation, and local and global area, timing, or power at an architecture level above RTL or gate-level synthesis; automatically generating a software development kit (SDK) and the associated firmware automatically to execute the computer readable code on the custom integrated circuit; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了系统和方法，以基于算法过程或代码作为输入自动设计定制集成电路，并且使用几乎不需要人为参与的高度自动化的工具。 该方法包括接收包括计算机可读代码和定制集成电路上的一个或多个约束的定制集成电路的规范; 自动生成最适合约束的计算机可读代码的计算机体系结构; 基于代码简档自动确定指令执行序列，并重新分配或延迟指令序列以在一个或多个处理块上扩展操作以减少热点; 连续评估和优化一个或多个因素，包括物理实现，以及在RTL或门级合成之上的架构级别的本地和全局区域，时序或功率; 自动生成软件开发工具包（SDK）和相关固件，以执行定制集成电路上的计算机可读代码; 为定制集成电路上的计算机可读代码自动生成相关的测试套件和向量; 并自动合成设计的架构并生成用于半导体制造的定制集成电路的计算机可读描述。

公开(公告)号：US08370784B2

公开(公告)日：2013-02-05

申请号：US12835621

申请日：2010-07-13

申请人： Satish Padmanabhan ,  Plus Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

发明人： Satish Padmanabhan ,  Plus Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5022 ,  G06F17/5045

摘要： Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed. The method includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; continuously evaluating and optimizing one or more factors including physical implementation, and local and global area, timing, or power at an architecture level above RTL or gate-level synthesis; automatically generating a software development kit (SDK) and the associated firmware automatically to execute the computer readable code on the custom integrated circuit; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了系统和方法，以基于算法过程或代码作为输入自动设计定制集成电路，并且使用几乎不需要人为参与的高度自动化的工具。 该方法包括接收包括计算机可读代码和定制集成电路上的一个或多个约束的定制集成电路的规范; 自动生成最适合约束的计算机可读代码的计算机体系结构; 基于代码简档自动确定指令执行序列，并重新分配或延迟指令序列以在一个或多个处理块上扩展操作以减少热点; 连续评估和优化一个或多个因素，包括物理实现，以及在RTL或门级合成之上的架构级别的本地和全局区域，时序或功率; 自动生成软件开发工具包（SDK）和相关固件，以执行定制集成电路上的计算机可读代码; 为定制集成电路上的计算机可读代码自动生成相关的测试套件和向量; 并自动合成设计的架构并生成用于半导体制造的定制集成电路的计算机可读描述。

公开(公告)号：US08561005B2

公开(公告)日：2013-10-15

申请号：US13452891

申请日：2012-04-22

申请人： Ananth Durbha ,  Pius Ng ,  Gary Oblock ,  Suresh Kadiyala ,  Satish Padmanabhan

发明人： Ananth Durbha ,  Pius Ng ,  Gary Oblock ,  Suresh Kadiyala ,  Satish Padmanabhan

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5045

摘要： Systems and methods are disclosed to automatically synthesize a custom integrated circuit by automatically generating an application specific instruction set processor architecture uniquely customized to the computer readable code with a compiler-in-the-loop to compile, assemble and link code for each processor architecture iteration, the processor architecture having one or more processing blocks on the IC executing one or more instructions; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 系统和方法被公开以通过自动地生成针对每个处理器架构迭代来编译，组合和链接代码的编译器在循环中独特地定制到计算机可读代码的应用特定指令集处理器架构来自动合成定制集成电路 所述处理器架构在所述IC上具有执行一个或多个指令的一个或多个处理块; 以及将生成的架构合成到用于半导体制造的定制集成电路的计算机可读描述中。