公开(公告)号：US5413950A

公开(公告)日：1995-05-09

申请号：US231461

申请日：1994-04-22

申请人： Anchor Chen ,  Min-Tzong Yang ,  Chen-Chiu Hsue ,  Gary Hong

发明人： Anchor Chen ,  Min-Tzong Yang ,  Chen-Chiu Hsue ,  Gary Hong

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/00 ,  H01L21/70

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/82

摘要： A new stacked capacitor structure having increased capacitance and a method of fabrication was accomplished. The capacitor stores data in the form of stored charge and together with a field effect transistor (MOSFET) make up the individual Dynamic Random Access Memory (DRAM) storage cells on a DRAM chip. The improved capacitor is fabricated using an electrically conducting layer in the bottom electrode of the capacitor, which is substantially different in composition from silicon. The conducting layer preferably being a refractory metal or a refactory metal silicides, such as, tungsten (W) or tungsten silicide (WSi). The bottom electrode is formed from a multilayer composed of a thin polysilicon layer, the conducting layer and an upper thicker polysilicon layer. Vertical capacitor sidewalls are formed from the upper polysilicon layer by photoresist masking and then etching to the conducting layer. The conducting layer provides an etch end point for accurately etching to the correct depth without over etching. This provides a repeatable and more manufacturable process. The stacked capacitor is then completed by depositing a high dielectric constant insulator layer over the bottom electrode and then forming the top capacitor electrode, thereby completing the stacked capacitor.

摘要翻译： 实现了具有增加的电容的新的堆叠电容器结构和制造方法。 电容器以存储电荷的形式存储数据，并与场效应晶体管（MOSFET）一起组成DRAM芯片上的单独的动态随机存取存储器（DRAM）存储单元。 改进的电容器使用电容器的底部电极中的导电层制造，其与硅的组成基本上不同。 导电层优选为难熔金属或重构金属硅化物，例如钨（W）或硅化钨（WSi）。 底部电极由由多晶硅薄层，导电层和较厚的多晶硅层构成的多层构成。 垂直电容器侧壁由上多晶硅层通过光刻胶掩模形成，然后蚀刻到导电层。 导电层提供蚀刻终点，用于在没有过蚀刻的情况下精确地蚀刻到正确的深度。 这提供了可重复和更可制造的过程。 然后通过在底部电极上沉​​积高介电常数绝缘体层然后形成顶部电容器电极来完成叠层电容器，由此完成叠层电容器。