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    Configurable System for Cancellation of the Mean Value of a Modulated Signal
    1.
    发明申请
    Configurable System for Cancellation of the Mean Value of a Modulated Signal 有权
    用于取消调制信号平均值的可配置系统

    公开(公告)号：US20120133406A1

    公开(公告)日：2012-05-31

    申请号：US12956324

    申请日：2010-11-30

    Applicant: Andrea Fant ,  Luca Sant ,  Patrick Vernei Torta ,  Lukas Doerrer

    Inventor： Andrea Fant ,  Luca Sant ,  Patrick Vernei Torta ,  Lukas Doerrer

    IPC: H03K5/01

    CPC classification number: H03D1/06 ,  H03D3/003 ,  H03D2200/0047 ,  H03D2200/005 ,  H03D2200/0052

    Abstract: Some embodiments of the invention relate to a DC offset correction circuit comprising a feedback loop having a DAC controlled by a reconfigurable ADC, which determines (e.g., tracks) the mean value of a modulated input signal. The circuit operates according to two phase process. In a first “pre-modulation” tracking phase, an input signal is tracked by the ADC, which is configured to output the input signal's mean value as a digital code equivalent to the input mean value. The output of the ADC is provided to a DAC, which provides an analog representation of the mean value to an adder that subtracts the mean value from the modulated input signal to generate a bipolar adjusted input signal. In a second “modulation” phase, the estimated mean value is held constant, so that the bipolar adjusted input signal may be provided to an activated modulation circuit for improved system performance.

    Abstract translation: 本发明的一些实施例涉及一种DC偏移校正电路，其包括具有由可重构ADC控制的DAC的反馈回路，该可重构ADC确定（例如，跟踪）调制输入信号的平均值。 电路根据两相工艺进行工作。 在第一个“预调制”跟踪阶段，ADC跟踪输入信号，ADC被配置为将输入信号的平均值输出为与输入平均值相当的数字码。 ADC的输出被提供给DAC，DAC向加法器提供平均值的模拟表示，该加法器从调制输入信号中减去平均值以产生双极调整的输入信号。 在第二“调制”阶段，估计的平均值保持不变，从而可以将双极调节的输入信号提供给激活的调制电路，以改善系统性能。

    Configurable system for cancellation of the mean value of a modulated signal
    2.
    发明授权
    Configurable system for cancellation of the mean value of a modulated signal 有权
    用于消除调制信号平均值的可配置系统

    公开(公告)号：US08901996B2

    公开(公告)日：2014-12-02

    申请号：US12956324

    申请日：2010-11-30

    Applicant: Andrea Fant ,  Luca Sant ,  Patrick Vernei Torta ,  Lukas Doerrer

    Inventor： Andrea Fant ,  Luca Sant ,  Patrick Vernei Torta ,  Lukas Doerrer

    IPC: H03D1/06 ,  H04L25/06 ,  H03D3/00

    CPC classification number: H03D1/06 ,  H03D3/003 ,  H03D2200/0047 ,  H03D2200/005 ,  H03D2200/0052

    Abstract: Some embodiments of the invention relate to a DC offset correction circuit comprising a feedback loop having a DAC controlled by a reconfigurable ADC, which determines (e.g., tracks) the mean value of a modulated input signal. The circuit operates according to two phase process. In a first “pre-modulation” tracking phase, an input signal is tracked by the ADC, which is configured to output the input signal's mean value as a digital code equivalent to the input mean value. The output of the ADC is provided to a DAC, which provides an analog representation of the mean value to an adder that subtracts the mean value from the modulated input signal to generate a bipolar adjusted input signal. In a second “modulation” phase, the estimated mean value is held constant, so that the bipolar adjusted input signal may be provided to an activated modulation circuit for improved system performance.

    Abstract translation: 本发明的一些实施例涉及一种DC偏移校正电路，其包括具有由可重构ADC控制的DAC的反馈回路，该可重构ADC确定（例如，跟踪）调制输入信号的平均值。 电路根据两相工艺进行工作。 在第一个“预调制”跟踪阶段，ADC跟踪输入信号，ADC被配置为将输入信号的平均值输出为与输入平均值相当的数字码。 ADC的输出被提供给DAC，DAC向加法器提供平均值的模拟表示，该加法器从调制输入信号中减去平均值以产生双极调整的输入信号。 在第二“调制”阶段，估计的平均值保持不变，从而可以将双极调节的输入信号提供给激活的调制电路，以改善系统性能。

    Square wave signal component cancellation
    5.
    发明授权
    Square wave signal component cancellation 有权
    方波信号分量消除

    公开(公告)号：US08358164B2

    公开(公告)日：2013-01-22

    申请号：US12956358

    申请日：2010-11-30

    Applicant: Andrea Fant ,  Luca Sant ,  Patrick Vernei Torta

    Inventor： Andrea Fant ,  Luca Sant ,  Patrick Vernei Torta

    IPC: H03L5/00

    CPC classification number: H04L25/063 ,  H03C1/06 ,  H03C2200/0079

    Abstract: Some embodiments of the invention a circuit configured to apply a time domain processing sequence to a modulated input signal to estimate a mean value of the modulated input signal and to subtract the estimated mean value from the modulated input signal, thereby removing the DC offset from the input signal. In one particular embodiment, the time domain processing sequence is based on integration and differentiation of a demodulated output signal. In such an embodiment, a circuit is configured to integrate a demodulated signal to generate an integrated signal having a triangular shaped output signal. The circuit then measures the slopes of the integrated signal, by differentiation of the triangular shaped integrated signal, and generates an appropriate DC offset correction signal based upon the measured slopes. The DC offset correction signal may be added on top of the actual input signal to cancel the unwanted DC offset component.

    Abstract translation: 本发明的一些实施例构成为将一个时域处理序列应用于调制输入信号以估计调制输入信号的平均值并从调制输入信号中减去估计平均值的电路，由此从该 输入信号。 在一个特定实施例中，时域处理序列基于解调输出信号的积分和微分。 在这种实施例中，电路被配置为对解调信号进行积分以产生具有三角形输出信号的积分信号。 然后，电路通过三角形积分信号的微分来测量积分信号的斜率，并且基于测量的斜率产生适当的DC偏移校正信号。 DC偏移校正信号可以被添加在实际输入信号之上，以消除不想要的DC偏移分量。

    Square Wave Signal Component Cancellation
    6.
    发明申请
    Square Wave Signal Component Cancellation 有权
    方波信号分量取消

    公开(公告)号：US20120133412A1

    公开(公告)日：2012-05-31

    申请号：US12956358

    申请日：2010-11-30

    Applicant: Andrea Fant ,  Luca Sant ,  Patrick Vernei Torta

    Inventor： Andrea Fant ,  Luca Sant ,  Patrick Vernei Torta

    IPC: H03L5/00

    CPC classification number: H04L25/063 ,  H03C1/06 ,  H03C2200/0079

    Abstract: Some embodiments of the invention a circuit configured to apply a time domain processing sequence to a modulated input signal to estimate a mean value of the modulated input signal and to subtract the estimated mean value from the modulated input signal, thereby removing the DC offset from the input signal. In one particular embodiment, the time domain processing sequence is based on integration and differentiation of a demodulated output signal. In such an embodiment, a circuit is configured to integrate a demodulated signal to generate an integrated signal having a triangular shaped output signal. The circuit then measures the slopes of the integrated signal, by differentiation of the triangular shaped integrated signal, and generates an appropriate DC offset correction signal based upon the measured slopes. The DC offset correction signal may be added on top of the actual input signal to cancel the unwanted DC offset component.

    Abstract translation: 本发明的一些实施例构成为将一个时域处理序列应用于调制输入信号以估计调制输入信号的平均值并从调制输入信号中减去估计平均值的电路，由此从该 输入信号。 在一个特定实施例中，时域处理序列基于解调输出信号的积分和微分。 在这种实施例中，电路被配置为对解调信号进行积分以产生具有三角形输出信号的积分信号。 然后，电路通过三角形积分信号的微分来测量积分信号的斜率，并且基于测量的斜率产生适当的DC偏移校正信号。 DC偏移校正信号可以被添加在实际输入信号之上，以消除不想要的DC偏移分量。

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