Starting circuit and method for the stable starting of a circuit arrangement with plural feedback control circuits
    1.
    发明授权
    Starting circuit and method for the stable starting of a circuit arrangement with plural feedback control circuits 有权
    用于具有多个反馈控制电路的电路布置的稳定启动的启动电路和方法

    公开(公告)号:US07903009B2

    公开(公告)日:2011-03-08

    申请号:US11588871

    申请日:2006-10-27

    Applicant: Lukas Doerrer

    Inventor: Lukas Doerrer

    CPC classification number: G05B7/02 H03M3/364 H03M3/438 H03M3/486 H03M3/49

    Abstract: In a method for starting a circuit arrangement an output signal of a circuit arrangement with interlinked feedback control circuits is utilized as a control variable for the feedback control circuits and an input signal for the circuit arrangement is damped for a predetermined time period during a starting phase of the circuit arrangement.

    Abstract translation: 在用于启动电路装置的方法中,利用具有互连反馈控制电路的电路装置的输出信号作为用于反馈控制电路的控制变量,并且用于电路装置的输入信号在启动阶段被衰减预定时间段 的电路布置。

    Control Apparatus and Method for Scrambling the Assignment of the References of a Quantizer in a Sigma-Delta Analogue/Digital Converter
    2.
    发明申请
    Control Apparatus and Method for Scrambling the Assignment of the References of a Quantizer in a Sigma-Delta Analogue/Digital Converter 有权
    用于对Sigma-Delta模拟/数字转换器中的量化器的参考的分配进行加扰的控制装置和方法

    公开(公告)号:US20060227027A1

    公开(公告)日:2006-10-12

    申请号:US11276802

    申请日:2006-03-15

    CPC classification number: H03M1/0668 H03M1/365 H03M3/424 H03M3/464

    Abstract: The control apparatus (8′) is used to dynamically assign N individual references to N individual comparators of a quantizer in a sigma-delta analogue/digital converter, the control apparatus (8′) generating a digital control signal (9′). The control apparatus (8′) has a storage means (12) for providing the value of the control signal (9′) at the time k−1, and a summation means (10) for summing the output signal Y of the quantizer with the stored value of the first control signal (9′) at the time k−1.

    Abstract translation: 控制装置(8')用于在Σ-Δ模拟/数字转换器中动态地将N个单独参考值分配给量化器的N个单独比较器,所述控制装置(8')产生数字控制信号(9')。 控制装置(8')具有用于在时刻k-1提供控制信号(9')的值的存储装置(12)和用于将量化器的输出信号Y与 在时间k-1处的第一控制信号(9')的存储值。

    Forward-amplifying filter circuit
    3.
    发明授权
    Forward-amplifying filter circuit 有权
    正向放大滤波电路

    公开(公告)号:US07119608B2

    公开(公告)日:2006-10-10

    申请号:US10926549

    申请日:2004-08-26

    Applicant: Lukas Doerrer

    Inventor: Lukas Doerrer

    CPC classification number: H03H11/1217

    Abstract: The invention relates to a forward-amplifying filter circuit which has an analogue filter with poles and zero points, having a first number of integrators which form the poles, which are arranged in series with one another and which each have an active component with a capacitance arranged in parallel therewith, having a second number of coefficients which form the zero points and which have at least one forward-amplifying path which contains a differentiating element, having a summing node whose input side is connected to the forward-amplifying paths of the zero points and whose output side is connected to the input of the last of the active components arranged in series. The invention also relates to an analog/digital converter circuit having such a filter circuit.

    Abstract translation: 本发明涉及一种具有极点和零点的模拟滤波器的正向放大滤波器电路,具有形成极点的第一数量的积分器,它们彼此串联布置,并且每个具有具有电容的有源分量 具有与第二数量的系数形成零点并且具有至少一个包含微分元件的前向放大路径,具有加法节点,其加法节点的输入端连接到零点的前向放大路径 点,其输出侧连接到串联布置的最后一个有源元件的输入。 本发明还涉及具有这种滤波器电路的模/数转换器电路。

    Forward-amplifying filter circuit
    4.
    发明申请
    Forward-amplifying filter circuit 有权
    正向放大滤波电路

    公开(公告)号:US20050052226A1

    公开(公告)日:2005-03-10

    申请号:US10926549

    申请日:2004-08-26

    Applicant: Lukas Doerrer

    Inventor: Lukas Doerrer

    CPC classification number: H03H11/1217

    Abstract: The invention relates to a forward-amplifying filter circuit which has an analogue filter with poles and zero points, having a first number of integrators which form the poles, which are arranged in series with one another and which each have an active component with a capacitance arranged in parallel therewith, having a second number of coefficients which form the zero points and which have at least one forward-amplifying path which contains a differentiating element, having a summing node whose input side is connected to the forward-amplifying paths of the zero points and whose output side is connected to the input of the last of the active components arranged in series. The invention also relates to an analog/digital converter circuit having such a filter circuit.

    Abstract translation: 本发明涉及一种具有极点和零点的模拟滤波器的正向放大滤波器电路,具有形成极点的第一数量的积分器,它们彼此串联布置,并且每个具有具有电容的有源分量 具有与第二数量的系数形成零点并且具有至少一个包含微分元件的前向放大路径,具有加法节点,其加法节点的输入端连接到零点的前向放大路径 点,其输出侧连接到串联布置的最后一个有源元件的输入。 本发明还涉及具有这种滤波器电路的模/数转换器电路。

    Receiver circuit
    5.
    发明授权
    Receiver circuit 有权
    接收电路

    公开(公告)号:US07983640B2

    公开(公告)日:2011-07-19

    申请号:US11645002

    申请日:2006-12-22

    Applicant: Lukas Doerrer

    Inventor: Lukas Doerrer

    CPC classification number: H04B1/30 H03M3/406 H03M3/424 H03M3/454

    Abstract: A receiver circuit for receiving an analog signal comprises a mixer device, a first integrator device coupled to the mixer device, a second integrator device following the first integrator device, a quantizer device, and first and second feedback digital/analog converters. The mixer device mixes the analog signal with a local-oscillator frequency and outputs a mixer current signal. The first integrator device generates a first intermediate signal by integrating the mixer current signal summed with a first feedback current signal, the second integrator device generates a quantizer input signal by integrating the first intermediate signal summed with a second feedback current signal, and the quantizer device generates a digital output signal by quantizing the quantizer input signal. The first feedback digital/analog converter converts the digital output signal into the first feedback current signal and the second feedback digital/analog converter converts the digital output signal into the second feedback current signal.

    Abstract translation: 用于接收模拟信号的接收器电路包括混频器装置,耦合到混频器装置的第一积分器装置,跟随第一积分器装置的第二积分器装置,量化器装置以及第一和第二反馈数/模转换器。 混频器设备将模拟信号与本地振荡器频率混合,并输出混频器电流信号。 第一积分器装置通过对与第一反馈电流信号相加的混频器电流信号进行积分来产生第一中间信号,第二积分器装置通过将与第二反馈电流信号相加的第一中间信号和量化器装置 通过量化量化器输入信号来产生数字输出信号。 第一反馈数/模转换器将数字输出信号转换成第一反馈电流信号,第二反馈数/模转换器将数字输出信号转换成第二反馈电流信号。

    Processing signals of a capacitive feedforward filter
    6.
    发明授权
    Processing signals of a capacitive feedforward filter 有权
    处理电容前馈滤波器的信号

    公开(公告)号:US07796071B2

    公开(公告)日:2010-09-14

    申请号:US12206647

    申请日:2008-09-08

    Applicant: Lukas Doerrer

    Inventor: Lukas Doerrer

    CPC classification number: H03M3/452 H03H11/1252 H03M3/43 H03M3/448

    Abstract: This disclosure relates to techniques and architecture for summing, sampling, and converting signals associated with a capacitive feedforward filter using a quantizer.

    Abstract translation: 本公开涉及用于使用量化器对与电容前馈滤波器相关联的信号求和,采样和转换信号的技术和架构。

    Filter With Capacitive Forward Coupling
    7.
    发明申请
    Filter With Capacitive Forward Coupling 有权
    电容式前向耦合滤波器

    公开(公告)号:US20080297387A1

    公开(公告)日:2008-12-04

    申请号:US11754822

    申请日:2007-05-29

    Applicant: Lukas Doerrer

    Inventor: Lukas Doerrer

    CPC classification number: H03M3/452 H03H11/1252 H03M3/43 H03M3/448

    Abstract: This disclosure relates to techniques and architecture for summing, sampling, and converting signals associated with a capacitive feedforward filter using a quantizer.

    Abstract translation: 本公开涉及用于使用量化器对与电容前馈滤波器相关联的信号求和,采样和转换信号的技术和架构。

    Multi-bit sigma/delta converter
    8.
    发明申请
    Multi-bit sigma/delta converter 有权
    多位Σ/Δ转换器

    公开(公告)号:US20070188362A1

    公开(公告)日:2007-08-16

    申请号:US11655772

    申请日:2007-01-19

    CPC classification number: H03M3/338 H03M3/424 H03M3/452 H03M3/454

    Abstract: A multi-bit sigma/delta converter for converting an analog input signal into a digital output signal comprises a filter device for filtering the analog input signal which is added to a feedback signal to form an intermediate signal. An integrator device for integrating the filtered intermediate signal added to an inner feedback signal forms a quantizer input signal. A quantizer device quantizes the quantizer input signal to form the digital output signal. An inner feedback digital/analog converter is provided for converting the digital output signal directly into the inner feedback signal. A DEM device for performing dynamic element matching on the digital output signal and providing a matched digital signal is provided and a feedback digital/analog converter for converting the matched digital signal into the feedback signal is implemented.

    Abstract translation: 用于将模拟输入信号转换为数字输出信号的多位Σ/Δ转换器包括滤波器装置,用于对加到反馈信号上的模拟输入信号进行滤波以形成中间信号。 用于对加到内反馈信号上的滤波后的中间信号进行积分的积分器装置形成量化器输入信号。 量化器装置量化量化器输入信号以形成数字输出信号。 提供内部反馈数字/模拟转换器,用于将数字输出信号直接转换成内部反馈信号。 提供了一种用于对数字输出信号执行动态元件匹配并提供匹配的数字信号的DEM装置,并且实现了用于将匹配的数字信号转换为反馈信号的反馈数/模转换器。

    Configurable System for Cancellation of the Mean Value of a Modulated Signal
    9.
    发明申请
    Configurable System for Cancellation of the Mean Value of a Modulated Signal 有权
    用于取消调制信号平均值的可配置系统

    公开(公告)号:US20120133406A1

    公开(公告)日:2012-05-31

    申请号:US12956324

    申请日:2010-11-30

    Abstract: Some embodiments of the invention relate to a DC offset correction circuit comprising a feedback loop having a DAC controlled by a reconfigurable ADC, which determines (e.g., tracks) the mean value of a modulated input signal. The circuit operates according to two phase process. In a first “pre-modulation” tracking phase, an input signal is tracked by the ADC, which is configured to output the input signal's mean value as a digital code equivalent to the input mean value. The output of the ADC is provided to a DAC, which provides an analog representation of the mean value to an adder that subtracts the mean value from the modulated input signal to generate a bipolar adjusted input signal. In a second “modulation” phase, the estimated mean value is held constant, so that the bipolar adjusted input signal may be provided to an activated modulation circuit for improved system performance.

    Abstract translation: 本发明的一些实施例涉及一种DC偏移校正电路,其包括具有由可重构ADC控制的DAC的反馈回路,该可重构ADC确定(例如,跟踪)调制输入信号的平均值。 电路根据两相工艺进行工作。 在第一个“预调制”跟踪阶段,ADC跟踪输入信号,ADC被配置为将输入信号的平均值输出为与输入平均值相当的数字码。 ADC的输出被提供给DAC,DAC向加法器提供平均值的模拟表示,该加法器从调制输入信号中减去平均值以产生双极调整的输入信号。 在第二“调制”阶段,估计的平均值保持不变,从而可以将双极调节的输入信号提供给激活的调制电路,以改善系统性能。

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