公开(公告)号：US08583049B2

公开(公告)日：2013-11-12

申请号：US12555376

申请日：2009-09-08

Applicant: Thomas E. Collins, III

Inventor： Thomas E. Collins, III

IPC: H04B7/00 ,  H04B17/00 ,  H04B1/10

CPC classification number: H03D7/1441 ,  H03D7/1458 ,  H03D7/1491 ,  H03D2200/0019 ,  H03D2200/0043 ,  H03D2200/0045 ,  H03D2200/0047 ,  H03D2200/0084 ,  H03D2200/0088

Abstract: Techniques are disclosed for optimization of RF converters. The techniques can be employed, for instance, in RF converters implemented in semiconductor materials (system-on-chip, or chip set) or with discrete components on a printed circuit board. In any such cases, the RF converter system can be configured with one or more actuators to adjust performance, one or more sensor to assess the performance (e.g., linearity of RF converter) and parameters of interest (e.g., ambient temperature, and a control block for controlling the sensors and actuators. The configuration allows the RF converter to autonomously self-optimize for linearity or other parameters of interest such as gain, noise figure, and dynamic range, across a broad range of variables.

Abstract translation: 公开了用于优化RF转换器的技术。 这些技术可以用于例如在半导体材料（片上系统或芯片组）中实施的RF转换器中，或者在印刷电路板上使用分立元件。 在任何这种情况下，RF转换器系统可以配置有一个或多个致动器来调整性能，一个或多个传感器来评估性能（例如，RF转换器的线性度）和感兴趣的参数（例如，环境温度和控制 用于控制传感器和执行器的模块，该配置允许RF转换器在广泛的变量范围内自主地优化线性度或其他感兴趣的参数，例如增益，噪声系数和动态范围。

公开(公告)号：US08532224B2

公开(公告)日：2013-09-10

申请号：US12735201

申请日：2008-12-19

Applicant: Remco Van De Beek ,  Domine Leenaerts ,  Charles Razzell ,  Jozef R. M. Ervoet

Inventor： Remco Van De Beek ,  Domine Leenaerts ,  Charles Razzell ,  Jozef R. M. Ervoet

IPC: H03C3/00

CPC classification number: H03D7/00 ,  H03D2200/0047 ,  H03D2200/0082 ,  H04L5/0007 ,  H04L27/0014 ,  H04L27/227 ,  H04L27/2601 ,  H04L27/364 ,  H04L2027/0016 ,  H04L2027/0022 ,  H04L2027/0032 ,  H04L2027/0065

Abstract: A signal processing circuit comprises a frequency up-conversion circuit (14, 60) for performing up-conversion with a first local oscillator frequency and a frequency down-conversion circuit (16) for performing down-conversion with a second local oscillator frequency. A digital signal processor (10) controls supply first signals representing a first complex signal to the up-conversion circuit, and receives second signals representing a second complex signal. The digital signal processor controls a compensation of I/Q mismatch of results of up-conversion and/or down-conversion. The digital signal processor (10) switches to a calibration mode for selecting a parameter of said compensation. In the calibration mode the first and second local oscillator frequencies have a frequency offset with respect to each other. The digital signal processor (10) measures an amplitude of a frequency component at a frequency corresponding to mismatch in one and not more than one of the results of up-conversion and/or down-conversion, and selects the parameter dependent on the amplitude.

Abstract translation: 信号处理电路包括用于以第一本地振荡器频率执行上变频的升频转换电路（14,60）和用于执行具有第二本机振荡器频率的下变频的降频转换电路（16）。 数字信号处理器（10）控制向上转换电路提供表示第一复信号的第一信号，并接收表示第二复信号的第二信号。 数字信号处理器控制上转换和/或下转换结果的I / Q不匹配的补偿。 数字信号处理器（10）切换到用于选择所述补偿的参数的校准模式。 在校准模式中，第一和第二本地振荡器频率相对于彼此具有频率偏移。 数字信号处理器（10）以对应于上变频和/或下变频结果中的一个且不超过一个失配的频率测量频率分量的幅度，并且根据幅度选择参数。

公开(公告)号：US20120133406A1

公开(公告)日：2012-05-31

申请号：US12956324

申请日：2010-11-30

Applicant: Andrea Fant ,  Luca Sant ,  Patrick Vernei Torta ,  Lukas Doerrer

Inventor： Andrea Fant ,  Luca Sant ,  Patrick Vernei Torta ,  Lukas Doerrer

IPC: H03K5/01

CPC classification number: H03D1/06 ,  H03D3/003 ,  H03D2200/0047 ,  H03D2200/005 ,  H03D2200/0052

Abstract: Some embodiments of the invention relate to a DC offset correction circuit comprising a feedback loop having a DAC controlled by a reconfigurable ADC, which determines (e.g., tracks) the mean value of a modulated input signal. The circuit operates according to two phase process. In a first “pre-modulation” tracking phase, an input signal is tracked by the ADC, which is configured to output the input signal's mean value as a digital code equivalent to the input mean value. The output of the ADC is provided to a DAC, which provides an analog representation of the mean value to an adder that subtracts the mean value from the modulated input signal to generate a bipolar adjusted input signal. In a second “modulation” phase, the estimated mean value is held constant, so that the bipolar adjusted input signal may be provided to an activated modulation circuit for improved system performance.

Abstract translation: 本发明的一些实施例涉及一种DC偏移校正电路，其包括具有由可重构ADC控制的DAC的反馈回路，该可重构ADC确定（例如，跟踪）调制输入信号的平均值。 电路根据两相工艺进行工作。 在第一个“预调制”跟踪阶段，ADC跟踪输入信号，ADC被配置为将输入信号的平均值输出为与输入平均值相当的数字码。 ADC的输出被提供给DAC，DAC向加法器提供平均值的模拟表示，该加法器从调制输入信号中减去平均值以产生双极调整的输入信号。 在第二“调制”阶段，估计的平均值保持不变，从而可以将双极调节的输入信号提供给激活的调制电路，以改善系统性能。

公开(公告)号：US08190117B2

公开(公告)日：2012-05-29

申请号：US12207785

申请日：2008-09-10

Applicant: Toshiya Mitomo ,  Osamu Watanabe

Inventor： Toshiya Mitomo ,  Osamu Watanabe

IPC: H04B1/26 ,  H04B1/28 ,  H01Q11/12

CPC classification number: H03D7/1441 ,  H03D7/1458 ,  H03D7/165 ,  H03D2200/0047 ,  H03D2200/0084

Abstract: A mixer circuit includes a voltage-to-current converter which converts a positive phase input voltage signal and a reversed phase input voltage signal input to a first input terminal and a second input terminal into a positive phase current signal and a reversed phase current signal, a switching circuit switches over the positive phase current signal and the reversed phase current signal according to a positive phase local signal and a reversed phase local signal, and generates a positive phase output current signal and a reversed phase output current signal, and an impedance element connected between the first common terminal and the second common terminal, having a relatively high impedance to a differential-mode signal between the positive phase current signal and the reversed phase current signal, and having a relatively low impedance to a common-mode signal between the positive phase current signal and the reversed phase current signal.

Abstract translation: 混频器电路包括电压 - 电流转换器，其将输入到第一输入端子和第二输入端子的正相输入电压信号和反相输入电压信号转换为正相电流信号和反相电流信号， 开关电路根据正相本地信号和反相本地信号切换正相电流信号和反相电流信号，并产生正相输出电流信号和反相输出电流信号，以及阻抗元件 连接在第一公共端子和第二公共端子之间，对正相电流信号和反相电流信号之间的差分模式信号具有相对较高的阻抗，并且具有相对较低的阻抗， 正相电流信号和反相电流信号。

公开(公告)号：US20120028594A1

公开(公告)日：2012-02-02

申请号：US12844961

申请日：2010-07-28

Applicant: YADUNANDANA RAO ,  CHARLES R. RUELKE ,  DARRELL J. STOGNER ,  RICHARD S. YOUNG

Inventor： YADUNANDANA RAO ,  CHARLES R. RUELKE ,  DARRELL J. STOGNER ,  RICHARD S. YOUNG

IPC: H04B1/16

CPC classification number: H04B1/30 ,  H03D3/009 ,  H03D2200/0047 ,  H03D2200/0082 ,  H03G3/3052

Abstract: An apparatus and method for demodulating an FM RF signal is presented. An Adaptive Differentiate Cross Multiply (ADCM) system in which the energy estimate of the desired on-channel RF is generated using adaptive filtering. The adaptive filter includes low pass filtering of the instantaneous energy estimate. The bandwidth of the LPF is adjusted in real time based on the received signal strength energy estimate, the periodicity of any changes in the energy estimate, AGC setting for the receiver, and/or the type of sub-audible signaling applied to the RF signal if known. After the bandwidth is set, the optimum filtered energy estimate is applied to the system to demodulate the received information free from distortion artifacts associated with IQ imbalance. A normalized signal in the ADCM system is clipped by a limiter whose clipping threshold is equal to a maximum gain of differentiators in the ADCM system.

Abstract translation: 提出了一种用于解调FM RF信号的装置和方法。 自适应差分交叉乘法（ADCM）系统，其中使用自适应滤波来生成期望的同信道RF的能量估计。 自适应滤波器包括瞬时能量估计的低通滤波。 基于接收到的信号强度能量估计，能量估计的任何变化的周期性，接收机的AGC设置和/或应用于RF信号的子听觉信号的类型，实时地调整LPF的带宽 如果已知。 在设置带宽之后，将最佳滤波能量估计值应用于系统以解调所接收到的信息，而不存在与IQ失衡相关的失真伪像。 ADCM系统中的归一化信号由限幅器限幅，其限幅阈值等于ADCM系统中微分器的最大增益。

公开(公告)号：US08000676B2

公开(公告)日：2011-08-16

申请号：US11942875

申请日：2007-11-20

Applicant: Hyun-Seok Kim ,  Woo-Nyun Kim

Inventor： Hyun-Seok Kim ,  Woo-Nyun Kim

IPC: H04B1/26

CPC classification number: H04B1/30 ,  H03D2200/0047 ,  H03D2200/0088

Abstract: A second intercept point (IP2) calibrator and a method for calibrating IP2 are disclosed. The IP2 calibrator and the method for calibrating IP2 remove any direct current (DC) offset by comparing a common-mode reference voltage with the common-mode voltage measured between a first output terminal and a second output terminal of a mixer, and calibrates the IP2 of the mixer by comparing the common-mode voltage with a calibration reference voltage. The calibration reference voltage is independent of the common-mode reference voltage and may be a quantized variable voltage generated according to digital control code.

Abstract translation: 公开了第二拦截点（IP2）校准器和校准IP2的方法。 IP2校准器和校准IP2的方法通过将共模参考电压与在混频器的第一输出端子和第二输出端子之间测量的共模电压进行比较来消除任何直流（DC）偏移，并校准IP2 通过将共模电压与校准参考电压进行比较来实现。 校准参考电压与共模参考电压无关，可以是根据数字控制代码生成的量化可变电压。

公开(公告)号：US07929060B2

公开(公告)日：2011-04-19

申请号：US11120377

申请日：2005-05-02

Applicant: Weijie Yun ,  Samuel Sheng

Inventor： Weijie Yun ,  Samuel Sheng

IPC: H04N5/63

CPC classification number: H03D3/008 ,  H03D7/165 ,  H03D2200/0047 ,  H04L25/061 ,  H04L27/063 ,  H04N5/44 ,  H04N5/455 ,  H04N5/50 ,  H04N5/63

Abstract: An integrated circuit device having a television signal tuner, video decoder and power control circuit. The television signal tuner selects one of a plurality of television channels, and the video decoder converts a television signal conveyed in the selected television channel into a video display signal. The power control circuit alternately enables and disables the television tuner to enable reception of a first portion of video information conveyed in the television signal and to disable reception of a second portion of the video information.

Abstract translation: 一种具有电视信号调谐器，视频解码器和功率控制电路的集成电路装置。 电视信号调谐器选择多个电视频道中的一个，并且视频解码器将在所选择的电视频道中传送的电视信号转换为视频显示信号。 功率控制电路交替地启用和禁用电视调谐器以能够接收在电视信号中传送的视频信息的第一部分，并且禁止接收视频信息的第二部分。

公开(公告)号：US07920832B2

公开(公告)日：2011-04-05

申请号：US11979084

申请日：2007-10-30

Applicant: Jan Craninckx

Inventor： Jan Craninckx

IPC: H04B1/40

CPC classification number: H04B1/30 ,  H03C3/406 ,  H03D7/145 ,  H03D7/1458 ,  H03D7/1483 ,  H03D7/165 ,  H03D2200/0047

Abstract: An electrical device comprises analog conversion circuitry having an input and an output. The electrical device is essentially provided for converting a first input signal within a first frequency range applied to the input to a first output signal within a second frequency range different from the first frequency range at the output. The electrical device further comprises a signal adding means for adding at least a portion of the first output signal as second input signal to the first input signal. The analog conversion circuitry is also capable of converting the second input signal, which is within the second frequency range, back to the first frequency range. Additionally, a characteristic deriving means is provided for deriving at least one characteristic of the electrical device from the frequency converted second input signal, which appears at the output of the analog conversion circuitry.

Abstract translation: 电气设备包括具有输入和输出的模拟转换电路。 电气设备基本上被设置用于将施加到输入端的第一频率范围内的第一输入信号转换成与输出端的第一频率范围不同的第二频率范围内的第一输出信号。 电气设备还包括信号添加装置，用于将第一输出信号的至少一部分作为第二输入信号添加到第一输入信号。 模拟转换电路还能够将处于第二频率范围内的第二输入信号转换回第一频率范围。 此外，提供了一种特征导出装置，用于从出现在模拟转换电路的输出端的频率转换的第二输入信号中导出电气装置的至少一个特性。

公开(公告)号：US07885626B2

公开(公告)日：2011-02-08

申请号：US12056576

申请日：2008-03-27

Applicant: Satoshi Tanaka ,  Kazuo Watanabe ,  Masao Hotta ,  Toyohiko Hongo ,  Taizo Yamawaki ,  Masumi Kasahara ,  Kumiko Takikawa

Inventor： Satoshi Tanaka ,  Kazuo Watanabe ,  Masao Hotta ,  Toyohiko Hongo ,  Taizo Yamawaki ,  Masumi Kasahara ,  Kumiko Takikawa

IPC: H04B1/06 ,  H04B1/10

CPC classification number: H04B1/30 ,  H03D2200/0047 ,  H03K21/16

Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.

Abstract translation: 适合较大规模集成的收发器采用直接转换接收，以减少滤波器的数量。 此外，通过利用分频器来为RF频带提供具有本地振荡信号的接收机和发射机来减少VCO的数量。 每个具有固定分频比的分频器用于产生用于接收机的局部振荡信号，而具有可切换分频比的分频器用于产生用于发射机的本地振荡信号。 另外，用于基带信号的可变增益放大器设置有DC偏移电压检测器和DC偏移消除电路，用于支持高速数据通信以通过消除用于偏移的反馈回路内的滤波器的干涉来实现DC偏移的快速消除 消除。

公开(公告)号：US07859270B2

公开(公告)日：2010-12-28

申请号：US12493357

申请日：2009-06-29

Applicant: Sherif H. K. Embabi ,  Alan R. Holden ,  Jason P. Jaehnig ,  Abdellatif Bellaouar

Inventor： Sherif H. K. Embabi ,  Alan R. Holden ,  Jason P. Jaehnig ,  Abdellatif Bellaouar

IPC: G01R35/00 ,  H04B1/26 ,  H04B17/00

CPC classification number: H03D7/1441 ,  H03D7/1433 ,  H03D7/1458 ,  H03D7/1466 ,  H03D2200/0047 ,  H03D2200/0088

Abstract: A passive CMOS differential mixer circuit with a mismatch correction circuit for balancing the electrical characteristics of the two output paths. Once the output paths of the differential circuit are balanced, or matched as closely as possible, second order intermodulation product generation can be inhibited or at least reduced to acceptable levels. The mismatch correction circuit receives a digital offset signal, and generates one or more voltage signals to be selectively applied to the signal paths of the passive differential mixer circuit. The voltage signals can be adjusted back gate bias voltages applied to the bulk terminals of selected transistors to adjust their threshold voltages, or the voltage signals can be adjusted common mode voltages applied directly to a selected signal path. Since the differential mixer circuit is passive, no DC current contribution to noise is generated. The switching transistors of the mixer circuit can be maintained at minimal dimensions to reduce switching signal drive loading, resulting in lower power consumption and higher operating frequencies than if larger switching transistors were use

Abstract translation: 一种具有用于平衡两个输出路径的电气特性的失配校正电路的无源CMOS差分混频器电路。 一旦差分电路的输出路径平衡或尽可能匹配，可以抑制二阶互调乘积的产生或至少降低到可接受的水平。 失配校正电路接收数字偏移信号，并产生一个或多个电压信号以选择性地施加到无源差分混频器电路的信号路径。 电压信号可以调节施加到所选晶体管的体积端子的反向栅极偏置电压以调整其阈值电压，或者可以将电压信号调整为直接施加到选定信号路径的共模电压。 由于差分混频器电路是无源的，所以不产生直流电流对噪声的贡献。 混合器电路的开关晶体管可以保持在最小的尺寸以减少开关信号驱动负载，导致比如果使用更大的开关晶体管时更低的功耗和更高的工作频率