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23 条记录 (耗时 0.027 秒)

    Electrostatic discharge failure avoidance through interaction between floorplanning and power routing
    1.
    发明授权
    Electrostatic discharge failure avoidance through interaction between floorplanning and power routing 失效
    通过布局规划和电源布线之间的相互作用来避免静电放电故障

    公开(公告)号：US07496877B2

    公开(公告)日：2009-02-24

    申请号：US11202275

    申请日：2005-08-11

    申请人： Andrew D. Huber ,  Ciaran J. Brennan ,  Paul E. Dunn ,  Scott W. Gould ,  Lin Lin ,  Erich C. Schanzenbach

    发明人： Andrew D. Huber ,  Ciaran J. Brennan ,  Paul E. Dunn ,  Scott W. Gould ,  Lin Lin ,  Erich C. Schanzenbach

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： An integrated system and method to achieve ESD robustness on an integrated circuit (IC) in a fully automated ASIC design environment is described. Electrical characteristics and electrical limits on the power network are translated to power route region constraints for each chip input/output (I/O) cell. Electrical limits on the signal network are translated into signal route region constraints for each chip I/O cell. These constraints are passed on to an I/O floorplanner (automatic placer of I/O cells) that analyzes trade-offs between these constraints. For I/O cells that can not be placed to satisfy both power and signal region constraints, the I/O floorplanner utilizes the knowledge of alternative power distribution structures to group I/Os and create local power grid structures that have the effect of relaxing the power region constraints. Instructions for creating these local power grid structures are passed on to the automatic power routing tool.

    摘要翻译： 描述了在完全自动化ASIC设计环境中实现集成电路（IC）上ESD稳定性的集成系统和方法。 电力网络上的电气特性和电气限制被转换为每个芯片输入/输出（I / O）单元的功率路由区域约束。 信号网络上的电气限制被转换为每个芯片I / O单元的信号路由区域约束。 这些约束被传递到分析这些限制之间的权衡的I / O平面布局（I / O单元的自动放置器）。 对于不能放置以满足功率和信号区域约束的I / O单元，I / O平面布置器利用替代功率分配结构的知识来分组I / O，并创建具有放松效果的局部电网结构 功率区域约束。 创建这些局部电网结构的说明将传递给自动电力布线工具。

    Method of wiring power service terminals to a power network in a semiconductor integrated circuit
    4.
    发明授权
    Method of wiring power service terminals to a power network in a semiconductor integrated circuit 失效
    将电力服务终端连接到半导体集成电路中的电力网络的方法

    公开(公告)号：US06493859B1

    公开(公告)日：2002-12-10

    申请号：US09682641

    申请日：2001-10-01

    申请人： Scott W. Gould ,  Philip S. Honsinger ,  Andrew D. Huber ,  Patrick M. Ryan

    发明人： Scott W. Gould ,  Philip S. Honsinger ,  Andrew D. Huber ,  Patrick M. Ryan

    IPC分类号： G06F1750

    CPC分类号： G06F17/5077

    摘要： Disclosed is a method of routing power from a power network to one or more power service terminals within a voltage island, comprising: dividing the power network into segments; creating power service terminal to segment connections based on a first set of criteria; removing selected power service terminal to segment connections based on a second set of criteria; and selecting one power service terminal to segment connection for each the power service terminal. The first criteria is includes power drop, wire length, wire size, wiring layer restrictions and the second criteria includes electro-migration, wire length and current criteria.

    摘要翻译： 公开了一种将电力从电力网络路由到电压岛内的一个或多个电力服务终端的方法，包括：将所述电力网络划分成段; 创建电力服务终端以基于第一组标准来分割连接; 移除所选电力服务终端以基于第二组标准来分段连接; 并选择一个电力服务终端来对每个电力服务终端进行分段连接。 第一个标准包括功率下降，电线长度，电线尺寸，布线层限制，第二个标准包括电迁移，电线长度和电流标准。

    Macro design techniques to accommodate chip level wiring and circuit placement across the macro
    7.
    发明授权
    Macro design techniques to accommodate chip level wiring and circuit placement across the macro 有权
    宏观设计技术，以适应芯片级布线和电路布局

    公开(公告)号：US06543040B1

    公开(公告)日：2003-04-01

    申请号：US09526198

    申请日：2000-03-15

    申请人： Thomas R. Bednar ,  Paul E. Dunn ,  Scott W. Gould ,  Jeannie H. Panner ,  Paul S. Zuchowski

    发明人： Thomas R. Bednar ,  Paul E. Dunn ,  Scott W. Gould ,  Jeannie H. Panner ,  Paul S. Zuchowski

    IPC分类号： G06F1750

    CPC分类号： G06F17/5068 ,  Y10S707/99931

    摘要： Macro design techniques are disclosed for facilitating subsequent stage wiring across the macro. Whitespace areas within the macro are rearranged to accommodate the wiring. The rearrangement may take the form of physical rearrangement of the whitespace areas into routing tracks extending from one side of the macro to another; shielding using, for example, macro power bussing and/or macro wiring; routing power busses to the rearranged whitespace; and/or inserting active circuits with pins accessible to the wiring. In a preferred embodiment, active circuits are placed into rearranged macro whitespace during the design of subsequent stages. The rearrangement of the whitespace facilitates the wiring across the macro so that slew rate and path delay requirements of the subsequent stage wiring can be maintained, without excessive buffering or rerouting of wiring.

    摘要翻译： 公开了宏观设计技术，以便于跨宏观的后续布线。 重新布置宏中的空白区域以适应布线。 重新布置可以采取将空白区域的物理重新布置成从宏的一侧延伸到另一侧的路由轨道的形式; 使用例如宏功率总线和/或宏布线进行屏蔽; 路由功率总线到重新排列的空格; 和/或插入具有可接线的引脚的有源电路。 在优选实施例中，在后续阶段的设计期间，将有源电路放置在重排的宏空白中。 空白的重新排列有助于宏观上的布线，使得可以保持后续级布线的压摆率和路径延迟要求，而不会过度缓冲或重新布线。

    Voltage island chip implementation
    8.
    发明授权
    Voltage island chip implementation 失效
    电压岛芯片实现

    公开(公告)号：US06883152B2

    公开(公告)日：2005-04-19

    申请号：US10867914

    申请日：2004-06-15

    申请人： Thomas R. Bednar ,  Scott W. Gould ,  David E. Lackey ,  Douglas W. Stout ,  Paul S. Zuchowski

    发明人： Thomas R. Bednar ,  Scott W. Gould ,  David E. Lackey ,  Douglas W. Stout ,  Paul S. Zuchowski

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5045

    摘要： A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.

    摘要翻译： 用于设计集成电路芯片的方法和结构提供芯片设计，并且根据电压要求的相似性和元件的功率状态的时序来分配芯片设计的元件以产生电压岛。 本发明输出包括每个电压岛的功率和定时信息的电压岛规格表; 并自动，无需用户干预，就可以合成电压岛的供电网络。

    Low-power critical error rate communications controller
    9.
    发明授权
    Low-power critical error rate communications controller 失效
    低功率关键错误率通信控制器

    公开(公告)号：US06802033B1

    公开(公告)日：2004-10-05

    申请号：US09286855

    申请日：1999-04-06

    申请人： Claude L. Bertin ,  Alvar A. Dean ,  Kenneth J. Goodnow ,  Scott W. Gould ,  Patrick E. Perry ,  Wilbur D. Pricer ,  William R. Tonti

    发明人： Claude L. Bertin ,  Alvar A. Dean ,  Kenneth J. Goodnow ,  Scott W. Gould ,  Patrick E. Perry ,  Wilbur D. Pricer ,  William R. Tonti

    IPC分类号： G06F1100

    CPC分类号： G06F11/10 ,  H04L1/0053

    摘要： A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is entered saving battery life. The low power error correction mechanism runs at a slower frequency and lower power than the high power mechanism and maintains the same data rate for the controller, thus saving power. Selecting the controller error (power) mode may be externally, such as by a person using a control dial on a cellular telephone when the voice data gets too noisy. Alternatively, the selection can be automatic, a critical error level detector internally making the selection.

    摘要翻译： 一种在通信控制器上动态修改错误恢复的方式，以在当前错误率条件允许的最低功耗模式下工作。 当操作条件良好并且检测到少量错误时，输入低功率错误检测/校正模式，从而节省电池寿命。 低功率误差校正机构运行频率较低，功率低于大功率机构，并为控制器保持相同的数据速率，从而节省功耗。 选择控制器错误（电源）模式可以是外部的，例如当语音数据太嘈杂时，人们在蜂窝电话上使用控制拨盘。 或者，选择可以是自动的，在内部进行选择的关键误差电平检测器。

    Method and apparatus for manufacturing diamond shaped chips
    10.
    发明授权
    Method and apparatus for manufacturing diamond shaped chips 有权
    用于制造菱形芯片的方法和装置

    公开(公告)号：US07961932B2

    公开(公告)日：2011-06-14

    申请号：US11865728

    申请日：2007-10-01

    申请人： Robert J. Allen ,  John M. Cohn ,  Scott W. Gould ,  Peter A. Habitz ,  Juergen Koehl ,  Gustavo E. Tellez ,  Ivan L. Wemple ,  Paul S. Zuchowski

    发明人： Robert J. Allen ,  John M. Cohn ,  Scott W. Gould ,  Peter A. Habitz ,  Juergen Koehl ,  Gustavo E. Tellez ,  Ivan L. Wemple ,  Paul S. Zuchowski

    IPC分类号： G06K9/00

    CPC分类号： H01L27/0207

    摘要： In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.

    摘要翻译： 在第一方面中，用于对晶片上的芯片进行成像的本发明的装置包括具有多个倾斜侧面的组合金刚石芯片图像和切口图像。 组合的金刚石芯片图像和切口图像包括金刚石芯片图像，其包括与金刚石芯片图像的至少一个对角线平行的多个芯片图像行，并且包括与金刚石芯片图像相邻的切痕图像。 切口图像包括平行于金刚石切片图像的至少一个对角线的至少一个切痕图像行。 该装置还包括从组合的金刚石片图像和切痕图像延伸到步进器的曝光场的至少周边的阻挡材料。 在第二方面，成像装置包括n侧多边形组合芯片图像和切口图像。 还提供了制造芯片的创造性方法和根据本发明方法制造的晶片。