System and method for implementing a fast file synchronization in a data processing system
    1.
    发明授权
    System and method for implementing a fast file synchronization in a data processing system 失效
    用于在数据处理系统中实现快速文件同步的系统和方法

    公开(公告)号:US07464237B2

    公开(公告)日:2008-12-09

    申请号:US11259898

    申请日:2005-10-27

    IPC分类号: G06F12/00

    摘要: A system and method for implementing a fast file synchronization in a data processing system. A memory management unit divides a file stored in system memory into a collection of data block groups. In response to a master (e.g., processing unit, peripheral, etc.) modifying a first data block group among the collection of data block groups, the memory management unit writes a first block group number associated with the first data block group to system memory. In response to a master modifying a second data block group, the memory management unit writes the first data block group to a hard disk drive and writes a second data block group number associated with the second data block group to system memory. In response to a request to update modified data block groups of the file stored in the system memory to the hard disk drive, the memory management unit writes the second data block to the hard disk drive.

    摘要翻译: 一种用于在数据处理系统中实现快速文件同步的系统和方法。 存储器管理单元将存储在系统存储器中的文件划分成数据块组的集合。 响应于在数据块组的集合中修改第一数据块组的主(例如,处理单元,外围设备等),存储器管理单元将与第一数据块组相关联的第一块组号写入系统存储器 。 响应于主修改第二数据块组,存储器管理单元将第一数据块组写入硬盘驱动器,并将与第二数据块组相关联的第二数据块组编号写入系统存储器。 响应于将存储在系统存储器中的文件的修改的数据块组更新到硬盘驱动器的请求,存储器管理单元将第二数据块写入硬盘驱动器。

    System and method for CPI scheduling on SMT processors
    2.
    发明申请
    System and method for CPI scheduling on SMT processors 有权
    SMT处理器CPI调度的系统和方法

    公开(公告)号:US20050086660A1

    公开(公告)日:2005-04-21

    申请号:US10671132

    申请日:2003-09-25

    IPC分类号: G06F9/46

    CPC分类号: G06F9/4881 G06F2209/483

    摘要: A system and method for identifying compatible threads in a Simultaneous Multithreading (SMT) processor environment is provided by calculating a performance metric, such as CPI, that occurs when two threads are running on the SMT processor. The CPI that is achieved when both threads were executing on the SMT processor is determined. If the CPI that was achieved is better than the compatibility threshold, then information indicating the compatibility is recorded. When a thread is about to complete, the scheduler looks at the run queue from which the completing thread belongs to dispatch another thread. The scheduler identifies a thread that is (1) compatible with the thread that is still running on the SMT processor (i.e., the thread that is not about to complete), and (2) ready to execute. The CPI data is continually updated so that threads that are compatible with one another are continually identified.

    摘要翻译: 通过计算在SMT处理器上运行两个线程时发生的性能度量(如CPI),可以提供用于识别同时多线程(SMT)处理器环境中的兼容线程的系统和方法。 确定在两个线程在SMT处理器上执行时实现的CPI。 如果实现的CPI优于兼容性阈值,则记录指示兼容性的信息。 当线程即将完成时,调度程序将查看完成线程所属的运行队列,以调度另一个线程。 调度程序标识(1)与SMT处理器上仍然运行的线程(即,即将完成的线程)兼容的线程,以及(2)准备执行。 持续更新CPI数据,以便不断地识别彼此兼容的线程。

    System and method for CPI load balancing in SMT processors
    3.
    发明申请
    System and method for CPI load balancing in SMT processors 失效
    SMT处理器中CPI负载平衡的系统和方法

    公开(公告)号:US20050081183A1

    公开(公告)日:2005-04-14

    申请号:US10671057

    申请日:2003-09-25

    IPC分类号: G06F9/44 G06F9/46

    CPC分类号: G06F9/5083

    摘要: A system and method for scheduling threads in a Simultaneous Multithreading (SMT) processor environment utilizing multiple SMT processors is provided. Poor performing threads that are being run on each of the SMT processors are identified. After being identified, the poor performing threads are moved to a different SMT processor. Data is captured regarding the performance of threads. In one embodiment, this data includes each threads' CPI value. When a thread is moved, data regarding the thread and its performance at the time it was moved is recorded along with a timestamp. The data regarding previous moves is used to determine whether a thread's performance is improved following the move.

    摘要翻译: 提供了一种利用多个SMT处理器的同时多线程(SMT)处理器环境中调度线程的系统和方法。 识别在每个SMT处理器上运行的执行不良线程。 被识别后,执行不良的线程被移动到不同的SMT处理器。 捕获关于线程性能的数据。 在一个实施例中,该数据包括每个线程的CPI值。 当线程移动时,与线程及其在移动时的性能相关的数据与时间戳一起被记录。 关于先前移动的数据用于确定线程的性能是否随着移动而改善。

    Implementing a fast file synchronization in a data processing system
    4.
    发明授权
    Implementing a fast file synchronization in a data processing system 失效
    在数据处理系统中实现快速文件同步

    公开(公告)号:US07861051B2

    公开(公告)日:2010-12-28

    申请号:US12143552

    申请日:2008-06-20

    IPC分类号: G06F12/00

    摘要: A system and method for implementing a fast file synchronization in a data processing system. A memory management unit divides a file stored in system memory into a collection of data block groups. In response to a master (e.g., processing unit, peripheral, etc.) modifying a first data block group among the collection of data block groups, the memory management unit writes a first block group number associated with the first data block group to system memory. In response to a master modifying a second data block group, the memory management unit writes the first data block group to a hard disk drive and writes a second data block group number associated with the second data block group to system memory. In response to a request to update modified data block groups of the file stored in the system memory to the hard disk drive, the memory management unit writes the second data block to the hard disk drive.

    摘要翻译: 一种用于在数据处理系统中实现快速文件同步的系统和方法。 存储器管理单元将存储在系统存储器中的文件划分成数据块组的集合。 响应于在数据块组的集合中修改第一数据块组的主(例如,处理单元,外围设备等),存储器管理单元将与第一数据块组相关联的第一块组号写入系统存储器 。 响应于主修改第二数据块组,存储器管理单元将第一数据块组写入硬盘驱动器,并将与第二数据块组相关联的第二数据块组编号写入系统存储器。 响应于将存储在系统存储器中的文件的修改的数据块组更新到硬盘驱动器的请求,存储器管理单元将第二数据块写入硬盘驱动器。

    Scheduling threads in a multi-processor computer
    5.
    发明授权
    Scheduling threads in a multi-processor computer 有权
    在多处理器计算机中调度线程

    公开(公告)号:US07831980B2

    公开(公告)日:2010-11-09

    申请号:US12055179

    申请日:2008-03-25

    IPC分类号: G06F9/46 G06F13/24

    CPC分类号: G06F9/4812

    摘要: Scheduling threads in a multi-processor computer system including establishing an interrupt threshold for a thread, where the interrupt threshold represents a maximum permissible number of interrupts during thread execution on a processor; executing the thread on a current processor, where the thread has thread affinity for one or more processors including the current processor; counting a number of interrupts during execution of the thread on the current processor; and removing thread affinity for the current processor in dependence upon the counted number of interrupts and the interrupt threshold.

    摘要翻译: 在多处理器计算机系统中调度线程,包括建立线程的中断阈值,其中中断阈值表示在处理器上执行线程期间的最大允许中断次数; 在当前处理器上执行线程,其中线程对于包括当前处理器的一个或多个处理器具有线程亲和性; 在当前处理器上的线程执行期间对多个中断进行计数; 并根据计数的中断次数和中断阈值去除当前处理器的线程亲和度。

    System and method for CPI load balancing in SMT processors
    6.
    发明授权
    System and method for CPI load balancing in SMT processors 失效
    SMT处理器中CPI负载平衡的系统和方法

    公开(公告)号:US07676808B2

    公开(公告)日:2010-03-09

    申请号:US11955503

    申请日:2007-12-13

    IPC分类号: G06F9/46

    CPC分类号: G06F9/5083

    摘要: A system and method for scheduling threads in a Simultaneous Multithreading (SMT) processor environment utilizing multiple SMT processors is provided. Poor performing threads that are being run on each of the SMT processors are identified. After being identified, the poor performing threads are moved to a different SMT processor. Data is captured regarding the performance of threads. In one embodiment, this data includes each threads' CPI value. When a thread is moved, data regarding the thread and its performance at the time it was moved is recorded along with a timestamp. The data regarding previous moves is used to determine whether a thread's performance is improved following the move.

    摘要翻译: 提供了一种利用多个SMT处理器的同时多线程(SMT)处理器环境中调度线程的系统和方法。 识别在每个SMT处理器上运行的执行不良线程。 被识别后,执行不良的线程被移动到不同的SMT处理器。 捕获关于线程性能的数据。 在一个实施例中,该数据包括每个线程的CPI值。 当线程移动时,与线程及其在移动时的性能相关的数据与时间戳一起被记录。 关于先前移动的数据用于确定线程的性能是否随着移动而改善。

    Optimized Preemption and Reservation of Software Locks
    7.
    发明申请
    Optimized Preemption and Reservation of Software Locks 失效
    优化抢占和预订软件锁

    公开(公告)号:US20080163217A1

    公开(公告)日:2008-07-03

    申请号:US12049304

    申请日:2008-03-15

    IPC分类号: G06F9/46

    CPC分类号: G06F9/526 G06F2209/522

    摘要: An approach is provided that reserves a software lock for a waiting thread is presented. When a software lock is released by a first thread, a second thread that is waiting for the same resource controlled by the software lock is woken up. In addition, a reservation to the software lock is established for the second thread. After the reservation is established, if the lock is available and requested by a thread other than the second thread, the requesting thread is denied, added to the wait queue, and put to sleep. In addition, the reservation is cleared. After the reservation has been cleared, the lock will be granted to the next thread to request the lock.

    摘要翻译: 提供了一种保留用于等待线程的软件锁的方法。 当软件锁由第一个线程释放时,等待软件锁定的相同资源的第二个线程被唤醒。 另外,针对第二线程建立对软件锁定的预约。 在建立预留之后,如果第二线程之外的线程可用并请求该锁,则请求线程被拒绝,被添加到等待队列中并进入休眠状态。 此外,预订已被清除。 预订清除后,锁将被授予下一个线程以请求锁定。

    System for delaying priority boost in a priority offset amount only after detecting of preemption event during access to critical section
    8.
    发明授权
    System for delaying priority boost in a priority offset amount only after detecting of preemption event during access to critical section 有权
    用于仅在检测到关键部分的访问期间的抢占事件之前延迟优先级偏移量中的优先级提升的系统

    公开(公告)号:US07380247B2

    公开(公告)日:2008-05-27

    申请号:US10626192

    申请日:2003-07-24

    IPC分类号: G06F13/18 G06F13/00

    CPC分类号: G06F9/52 G06F9/4818

    摘要: A system and method is provided for delaying a priority boost of an execution thread. When a thread prepares to enter a critical section of code, such as when the thread utilizes a shared system resource, a user mode accessible data area is updated indicating that the thread is in a critical section and, if the kernel receives a preemption event, the priority boost that the thread should receive. If the kernel receives a preemption event before the thread finishes the critical section, the kernel applies the priority boost on behalf of the thread. Often, the thread will finish the critical section without having to have its priority actually boosted. If the thread does receive an actual priority boost then, after the critical section is finished, the kernel resets the thread's priority to a normal level.

    摘要翻译: 提供了一种用于延迟执行线程的优先级提升的系统和方法。 当线程准备进入代码的关键部分时,例如当线程利用共享系统资源时,更新用户模式可访问数据区域,指示线程处于关键部分,并且如果内核接收到抢占事件, 线程应该接收的优先级提升。 如果内核在线程完成关键部分之前收到抢占事件,则内核将代表线程应用优先级提升。 通常,线程将完成关键部分,而无需实际提升优先级。 如果线程确实接收到实际的优先级提升,那么在关键部分完成之后,内核会将线程的优先级重置为正常级别。

    System and method for delayed priority boost
    9.
    发明申请
    System and method for delayed priority boost 失效
    用于延迟优先级提升的系统和方法

    公开(公告)号:US20080072228A1

    公开(公告)日:2008-03-20

    申请号:US11943649

    申请日:2007-11-21

    IPC分类号: G06F9/46

    CPC分类号: G06F9/52 G06F9/4818

    摘要: A system and method is provided for delaying a priority boost of an execution thread. When a thread prepares to enter a critical section of code, such as when the thread utilizes a shared system resource, a user mode accessible data area is updated indicating that the thread is in a critical section and, if the kernel receives a preemption event, the priority boost that the thread should receive. If the kernel receives a preemption event before the thread finishes the critical section, the kernel applies the priority boost on behalf of the thread. Often, the thread will finish the critical section without having to have its priority actually boosted. If the thread does receive an actual priority boost then, after the critical section is finished, the kernel resets the thread's priority to a normal level.

    摘要翻译: 提供了一种用于延迟执行线程的优先级提升的系统和方法。 当线程准备进入代码的关键部分时,例如当线程利用共享系统资源时,更新用户模式可访问数据区域,指示线程处于关键部分,并且如果内核接收到抢占事件, 线程应该接收的优先级提升。 如果内核在线程完成关键部分之前收到抢占事件,则内核将代表线程应用优先级提升。 通常,线程将完成关键部分,而无需实际提升优先级。 如果线程确实接收到实际的优先级提升,那么在关键部分完成之后,内核会将线程的优先级重置为正常级别。

    System, application and method of reducing cache thrashing in a multi-processor with a shared cache on which a disruptive process is executing
    10.
    发明申请
    System, application and method of reducing cache thrashing in a multi-processor with a shared cache on which a disruptive process is executing 审中-公开
    在具有破坏性进程正在执行的共享缓存的多处理器中减少缓存颠簸的系统,应用和方法

    公开(公告)号:US20060036810A1

    公开(公告)日:2006-02-16

    申请号:US10916984

    申请日:2004-08-12

    IPC分类号: G06F12/00 G06F12/14

    CPC分类号: G06F9/5027 G06F2209/5018

    摘要: A system, apparatus and method of reducing cache thrashing in a multi-processor with a shared cache executing a disruptive process (i.e., a thread that has a poor cache affinity or a large cache footprint) are provided. When a thread is dispatched for execution, a table is consulted to determine whether the dispatched thread is a disruptive thread. If so, a system idle process is dispatched to the processor sharing a cache with the processor executing the disruptive thread. Since the system idle process may not use data intensively, cache thrashing may be avoided.

    摘要翻译: 提供了一种使用执行破坏性过程的共享高速缓存(即,具有差的缓存关联性或大的缓存占用空间的线程)的多处理器中的缓存颠簸的系统,装置和方法。 当一个线程被调度执行时,查询一个表以确定被调度的线程是否是一个中断线程。 如果是这样,系统空闲进程将被分配到与执行中断线程的处理器共享高速缓存的处理器。 由于系统空闲进程可能不会集中使用数据,因此可以避免缓存抖动。