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    Method of efficient gradient computation
    1.
    发明授权
    Method of efficient gradient computation 失效
    高效梯度计算方法

    公开(公告)号：US5886908A

    公开(公告)日：1999-03-23

    申请号：US825278

    申请日：1997-03-27

    申请人： Andrew Roger Conn ,  Rudolf Adriaan Haring ,  Chandramouli Visweswariah

    发明人： Andrew Roger Conn ,  Rudolf Adriaan Haring ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/5036 ,  G06F17/5063

    摘要： A method of efficient computation of gradients of a merit function of a system includes the steps of: specifying at least one parameter for which the gradients with respect to the at least one parameter are desired; specifying the merit function of interest in terms of observable measurements of the system; either solving or simulating the system to determine values of the measurements; expressing the gradients of the merit function as the gradient of a weighted sum of measurements; forming an appropriately configured adjoint system; and either solving or simulating the adjoint system to simultaneously determine the gradients of the merit function with respect to the at least one parameter by employing a single adjoint analysis. Preferably, the system may be modeled by a set of equations comprising at least one of the following: a nonlinear set of equations, a linear set of equations, a set of linear partial differential equations, a set of nonlinear partial differential equations, a set of linear differential algebraic equations or a set of nonlinear differential algebraic equations. Further, the system of interest may be a network and, preferably, may be an electrical circuit. Still further, elements of the adjoint network and excitations of the adjoint network are determined in order to obtain the gradients of the merit function by employing a single adjoint analysis. It is to be appreciated that, in a preferred embodiment, the gradients of merit function are computed for the purpose of optimization and the merit function may be either a Lagrangian merit function or an augmented Lagrangian merit function.

    摘要翻译： 一种有效计算系统的优值函数的梯度的方法包括以下步骤：指定至少一个参数，该参数相对于至少一个参数的梯度是期望的; 根据系统的可观测量指定感兴趣的优点功能; 解决或模拟系统以确定测量值; 将优值函数的梯度表示为加权求和和的梯度; 形成适当配置的伴随系统; 并且通过采用单一伴随分析来解决或模拟伴随系统以同时确定关于至少一个参数的优值函数的梯度。 优选地，可以通过包括以下至少一个的一组方程来建模系统：非线性方程组，线性方程组，一组线性偏微分方程，一组非线性偏微分方程，一组 的线性微分代数方程或一组非线性微分代数方程。 此外，感兴趣的系统可以是网络，并且优选地可以是电路。 此外，确定伴随网络的元素和伴随网络的激励，以便通过采用单个伴随分析来获得优值函数的梯度。 应当理解，在优选实施例中，为优化目的而计算优值函数的梯度，并且优值函数可以是拉格朗日优值函数或增强的拉格朗日优值函数。

    Method for incorporating noise considerations in automatic circuit optimization
    2.
    发明授权
    Method for incorporating noise considerations in automatic circuit optimization 失效
    将噪声考虑纳入自动电路优化的方法

    公开(公告)号：US5999714A

    公开(公告)日：1999-12-07

    申请号：US56430

    申请日：1998-04-07

    申请人： Andrew Roger Conn ,  Rudolf Adriaan Haring ,  Chandramouli Visweswariah

    发明人： Andrew Roger Conn ,  Rudolf Adriaan Haring ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/5036 ,  G06F17/5063

    摘要： A method of incorporating noise considerations during circuit optimization includes the steps of: specifying a circuit schematic to be optimized; specifying at least one noise criterion as a noise measurement, including the signal to be checked for noise, the sub-interval of time of interest, and the maximum allowable noise deviation; providing each noise criterion as either a semi-infinite constraint or a semi-infinite objective function; specifying at least one variable of the optimization; converting the semi-infinite noise constraints and the semi-infinite noise objective functions into time-integral equality constraints; optionally, if required, providing additional optimization criteria other than noise as, for each such criterion, either objective functions or constraints; creating a merit function to be minimized to solve the optimization problem; simulating the circuit in the time-domain; computing the values of the objective functions and constraints; efficiently computing the gradients of the merit function of the optimizer (including contributions of all objective functions and constraints and the time-integrals representing noise considerations) preferably by means of a single adjoint analysis; iteratively providing the constraint values, the objective function values and the gradients of the merit function to a nonlinear optimizer; and continuing the optimization iterations to convergence.

    摘要翻译： 在电路优化期间引入噪声考虑的方法包括以下步骤：指定要优化的电路原理图; 将至少一个噪声标准指定为噪声测量，包括要检查噪声的信号，感兴趣的时间的次间隔和最大允许噪声偏差; 将每个噪声标准提供为半无限约束或半无限目标函数; 指定优化的至少一个变量; 将半无限噪声约束和半无限噪声目标函数转换为时间积分等式约束; 可选地，如果需要，提供除噪声之外的附加优化标准，对于每个这样的标准，目标函数或约束; 创建优化函数以最小化以解决优化问题; 在时域模拟电路; 计算目标函数和约束的值; 优选地通过单个伴随分析来优化优化器的优值函数的梯度（包括所有目标函数和约束的贡献以及表示噪声考虑的时间积分）; 将优化函数的约束值，目标函数值和梯度迭代地提供给非线性优化器; 并继续优化迭代来收敛。

    Method and apparatus for generating test patterns for use in at-speed testing
    5.
    发明授权
    Method and apparatus for generating test patterns for use in at-speed testing 有权
    用于生成用于速度测试的测试模式的方法和装置

    公开(公告)号：US08359565B2

    公开(公告)日：2013-01-22

    申请号：US13439188

    申请日：2012-04-04

    申请人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    发明人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    IPC分类号： G06F17/50 ,  G06F11/22

    CPC分类号： G01R31/318328 ,  G01R31/318342

    摘要： In one embodiment, the invention is a method and apparatus generating test patterns for use in at-speed testing. One embodiment of a method for use by a general purpose computing device that is configured to generate a set of test patterns with which to test an integrated circuit chip includes receiving, by an input device of the general purpose computing device, statistical timing information relating to the integrated circuit chip and a logic circuit of the integrated circuit chip and generating, by a processor of the general purpose computing device, the set of test patterns in accordance with the statistical timing information while simultaneously selecting a set of paths on which to test the set of test patterns.

    摘要翻译： 在一个实施例中，本发明是产生用于在速测试中的测试图案的方法和装置。 由通用计算设备使用的方法的一个实施例被配置为生成用于测试集成电路芯片的一组测试图案，包括由通用计算设备的输入设备接收与 所述集成电路芯片和所述集成电路芯片的逻辑电路，并且由所述通用计算设备的处理器根据所述统计定时信息生成所述一组测试图案，同时选择一组在其上测试所述的路径 一套测试模式。

    Moment-based characterization waveform for static timing analysis
    6.
    发明授权
    Moment-based characterization waveform for static timing analysis 有权
    用于静态时序分析的基于时刻的表征波形

    公开(公告)号：US08359563B2

    公开(公告)日：2013-01-22

    申请号：US12542042

    申请日：2009-08-17

    申请人： Soroush Abbaspour ,  Peter Feldmann ,  David Ling ,  Chandramouli Visweswariah

    发明人： Soroush Abbaspour ,  Peter Feldmann ,  David Ling ,  Chandramouli Visweswariah

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/84

    摘要： In one embodiment, the invention is a moment-based characterization waveform for static timing analysis. One embodiment of a method for mapping a timing waveform associated with a gate of an integrated circuit to a characterization waveform includes using a processor to perform steps including: computing one or more moments of the timing waveform and defining the characterization waveform in accordance with the moments.

    摘要翻译： 在一个实施例中，本发明是用于静态时序分析的基于时刻的表征波形。 用于将与集成电路的栅极相关联的定时波形映射到表征波形的方法的一个实施例包括使用处理器执行步骤，包括：计算定时波形的一个或多个时刻并根据时刻定义表征波形 。

    Method and apparatus for selecting paths for use in at-speed testing
    8.
    发明授权
    Method and apparatus for selecting paths for use in at-speed testing 有权
    用于选择在速度测试中使用的路径的方法和装置

    公开(公告)号：US08340939B2

    公开(公告)日：2012-12-25

    申请号：US12610090

    申请日：2009-10-30

    申请人： Yiyu Shi ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    发明人： Yiyu Shi ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    IPC分类号： G01R31/00

    CPC分类号： G01R31/31835

    摘要： In one embodiment, the invention is a method and apparatus for selecting paths for use in at-speed testing. One embodiment of a method for selecting a set of n paths with which to test an integrated circuit chip includes: organizing the set of n paths into a plurality of sub-sets, receiving a new candidate path, and adding the new candidate path to one of the sub-sets when the new candidate path improves the process coverage metric of the sub-sets.

    摘要翻译： 在一个实施例中，本发明是用于选择在速度测试中使用的路径的方法和装置。 用于选择用于测试集成电路芯片的n个路径的集合的方法的一个实施例包括：将n个路径的集合组织成多个子集，接收新的候选路径，并将新的候选路径添加到一个 当新的候选路径改进子集的过程覆盖度量时，子集的子集。

    Method and apparatus for efficient incremental statistical timing analysis and optimization
    9.
    发明授权
    Method and apparatus for efficient incremental statistical timing analysis and optimization 有权
    用于高效增量统计时序分析和优化的方法和装置

    公开(公告)号：US08104005B2

    公开(公告)日：2012-01-24

    申请号：US12244512

    申请日：2008-10-02

    申请人： Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    发明人： Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/10 ,  G06F2217/84

    摘要： In one embodiment, the invention is a method and apparatus for efficient incremental statistical timing analysis and optimization. One embodiment of a method for determining an incremental extrema of n random variables, given a change to at least one of the n random variables, includes obtaining the n random variables, obtaining a first extrema for the n random variables, where the first extrema is an extrema computed prior to the change to the at least one of the n random variables, removing the at least one of the n random variables to form an (n−1) subset, computing a second extrema for the (n−1) subset in accordance with the first extrema and the at least one of the n random variables, and outputting a new extrema of the n random variables incrementally based on the extrema of the (n−1) subset and the at least one of the n random variables that changed.

    摘要翻译： 在一个实施例中，本发明是一种用于有效增量统计时序分析和优化的方法和装置。 给定对n个随机变量中的至少一个的改变的用于确定n个随机变量的增量极值的方法的一个实施例包括获得n个随机变量，获得n个随机变量的第一极值，其中第一极值是 在对所述n个随机变量中的至少一个随机变量进行改变之前计算的极值，去除所述n个随机变量中的所述至少一个以形成（n-1）子集，计算所述（n-1）子集的第二极值 根据第一极值和n个随机变量中的至少一个，并且基于第（n-1）个子集的极值和n个随机变量中的至少一个来递增地输出n个随机变量的新的极值 改变了。