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    Method of efficient gradient computation
    1.
    发明授权
    Method of efficient gradient computation 失效
    高效梯度计算方法

    公开(公告)号：US5886908A

    公开(公告)日：1999-03-23

    申请号：US825278

    申请日：1997-03-27

    申请人： Andrew Roger Conn ,  Rudolf Adriaan Haring ,  Chandramouli Visweswariah

    发明人： Andrew Roger Conn ,  Rudolf Adriaan Haring ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/5036 ,  G06F17/5063

    摘要： A method of efficient computation of gradients of a merit function of a system includes the steps of: specifying at least one parameter for which the gradients with respect to the at least one parameter are desired; specifying the merit function of interest in terms of observable measurements of the system; either solving or simulating the system to determine values of the measurements; expressing the gradients of the merit function as the gradient of a weighted sum of measurements; forming an appropriately configured adjoint system; and either solving or simulating the adjoint system to simultaneously determine the gradients of the merit function with respect to the at least one parameter by employing a single adjoint analysis. Preferably, the system may be modeled by a set of equations comprising at least one of the following: a nonlinear set of equations, a linear set of equations, a set of linear partial differential equations, a set of nonlinear partial differential equations, a set of linear differential algebraic equations or a set of nonlinear differential algebraic equations. Further, the system of interest may be a network and, preferably, may be an electrical circuit. Still further, elements of the adjoint network and excitations of the adjoint network are determined in order to obtain the gradients of the merit function by employing a single adjoint analysis. It is to be appreciated that, in a preferred embodiment, the gradients of merit function are computed for the purpose of optimization and the merit function may be either a Lagrangian merit function or an augmented Lagrangian merit function.

    摘要翻译： 一种有效计算系统的优值函数的梯度的方法包括以下步骤：指定至少一个参数，该参数相对于至少一个参数的梯度是期望的; 根据系统的可观测量指定感兴趣的优点功能; 解决或模拟系统以确定测量值; 将优值函数的梯度表示为加权求和和的梯度; 形成适当配置的伴随系统; 并且通过采用单一伴随分析来解决或模拟伴随系统以同时确定关于至少一个参数的优值函数的梯度。 优选地，可以通过包括以下至少一个的一组方程来建模系统：非线性方程组，线性方程组，一组线性偏微分方程，一组非线性偏微分方程，一组 的线性微分代数方程或一组非线性微分代数方程。 此外，感兴趣的系统可以是网络，并且优选地可以是电路。 此外，确定伴随网络的元素和伴随网络的激励，以便通过采用单个伴随分析来获得优值函数的梯度。 应当理解，在优选实施例中，为优化目的而计算优值函数的梯度，并且优值函数可以是拉格朗日优值函数或增强的拉格朗日优值函数。

    Method for incorporating noise considerations in automatic circuit optimization
    2.
    发明授权
    Method for incorporating noise considerations in automatic circuit optimization 失效
    将噪声考虑纳入自动电路优化的方法

    公开(公告)号：US5999714A

    公开(公告)日：1999-12-07

    申请号：US56430

    申请日：1998-04-07

    申请人： Andrew Roger Conn ,  Rudolf Adriaan Haring ,  Chandramouli Visweswariah

    发明人： Andrew Roger Conn ,  Rudolf Adriaan Haring ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/5036 ,  G06F17/5063

    摘要： A method of incorporating noise considerations during circuit optimization includes the steps of: specifying a circuit schematic to be optimized; specifying at least one noise criterion as a noise measurement, including the signal to be checked for noise, the sub-interval of time of interest, and the maximum allowable noise deviation; providing each noise criterion as either a semi-infinite constraint or a semi-infinite objective function; specifying at least one variable of the optimization; converting the semi-infinite noise constraints and the semi-infinite noise objective functions into time-integral equality constraints; optionally, if required, providing additional optimization criteria other than noise as, for each such criterion, either objective functions or constraints; creating a merit function to be minimized to solve the optimization problem; simulating the circuit in the time-domain; computing the values of the objective functions and constraints; efficiently computing the gradients of the merit function of the optimizer (including contributions of all objective functions and constraints and the time-integrals representing noise considerations) preferably by means of a single adjoint analysis; iteratively providing the constraint values, the objective function values and the gradients of the merit function to a nonlinear optimizer; and continuing the optimization iterations to convergence.

    摘要翻译： 在电路优化期间引入噪声考虑的方法包括以下步骤：指定要优化的电路原理图; 将至少一个噪声标准指定为噪声测量，包括要检查噪声的信号，感兴趣的时间的次间隔和最大允许噪声偏差; 将每个噪声标准提供为半无限约束或半无限目标函数; 指定优化的至少一个变量; 将半无限噪声约束和半无限噪声目标函数转换为时间积分等式约束; 可选地，如果需要，提供除噪声之外的附加优化标准，对于每个这样的标准，目标函数或约束; 创建优化函数以最小化以解决优化问题; 在时域模拟电路; 计算目标函数和约束的值; 优选地通过单个伴随分析来优化优化器的优值函数的梯度（包括所有目标函数和约束的贡献以及表示噪声考虑的时间积分）; 将优化函数的约束值，目标函数值和梯度迭代地提供给非线性优化器; 并继续优化迭代来收敛。

    High performance registers for pulsed logic
    3.
    发明授权
    High performance registers for pulsed logic 失效
    用于脉冲逻辑的高性能寄存器

    公开(公告)号：US5926487A

    公开(公告)日：1999-07-20

    申请号：US583297

    申请日：1996-01-05

    申请人： Terry Ivan Chappell ,  Michael Kevin Ciraula ,  Max Eduardo De Ycaza ,  Sang Hoo Dhong ,  Rudolf Adriaan Haring ,  Talal Kamel Jaber ,  Mark Samson Milshtein ,  Pho Hoang Nguyen ,  Edward Seewann

    发明人： Terry Ivan Chappell ,  Michael Kevin Ciraula ,  Max Eduardo De Ycaza ,  Sang Hoo Dhong ,  Rudolf Adriaan Haring ,  Talal Kamel Jaber ,  Mark Samson Milshtein ,  Pho Hoang Nguyen ,  Edward Seewann

    IPC分类号： G01R31/3185 ,  G01R31/28

    CPC分类号： G01R31/31853

    摘要： A high performance register that can be used as a pipelined register in logic chips that are designed using a pulsed logic methodology is described. The register features minimal setup time, pulse catching and pulse launching. The register circuitry complies with and implements a circuit-level test methodology for pulsed logic that features the ability to inhibit the reset of pulses, to force resets and to operate the circuits in a pseudo static mode. The register also complies with the level sensitive scan design (LSSD) methodology. Also described is a state-holding static master-slave register that complies with a pulsed logic design methodology, the register exhibiting an automatic power reduction feature and a simplified modular register bit design which can easily be adapted to either static domino or pulsed logic. The register is also LSSD compliant. Also described is the means and method for allowing static transmission gate input registers to comply with the static evaluate test mode. The automatic power reduction feature can be extended to downstream logic.

    摘要翻译： 描述了可以用作使用脉冲逻辑方法设计的逻辑芯片中的流水线寄存器的高性能寄存器。 寄存器具有最小的建立时间，脉冲捕获和脉冲启动。 寄存器电路符合并实施脉冲逻辑的电路级测试方法，该方法具有禁止脉冲复位的能力，强制复位和以伪静态模式操作电路。 寄存器还符合级别敏感扫描设计（LSSD）方法。 还描述了一种符合脉冲逻辑设计方法的状态保持静态主从寄存器，该寄存器具有自动功率降低特征和简化的模块寄存器位设计，其可以容易地适用于静态多米诺或脉冲逻辑。 该寄存器也符合LSSD标准。 还描述了允许静态传输门输入寄存器符合静态评估测试模式的手段和方法。 自动降功能可扩展到下游逻辑。