公开(公告)号：US08558318B2

公开(公告)日：2013-10-15

申请号：US13007098

申请日：2011-01-14

申请人： Angelo Pinto ,  Frank S Johnson ,  Benjamin P McKee ,  Shaofeng Yu

发明人： Angelo Pinto ,  Frank S Johnson ,  Benjamin P McKee ,  Shaofeng Yu

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L27/0928 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/7833

摘要： Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as amorphization and templated recrystallization (ATR) have disadvantages for fabrication of deep submicron CMOS. This invention is a method of forming an integrated circuit (IC) which has (100) and (110)-oriented regions. The method forms a directly bonded silicon (DSB) layer of (110)-oriented silicon on a (100)-oriented substrate. The DSB layer is removed in the NMOS regions and a (100)-oriented silicon layer is formed by selective epitaxial growth (SEG), using the substrate as the seed layer. NMOS transistors are formed on the SEG layer, while PMOS transistors are formed on the DSB layer. An integrated circuit formed with the inventive method is also disclosed.

公开(公告)号：US07892908B2

公开(公告)日：2011-02-22

申请号：US12343794

申请日：2008-12-24

申请人： Angelo Pinto ,  Frank S. Johnson ,  Benjamin P. McKee ,  Shaofeng Yu

发明人： Angelo Pinto ,  Frank S. Johnson ,  Benjamin P. McKee ,  Shaofeng Yu

IPC分类号： H01L21/8238 ,  H01L21/335

CPC分类号： H01L27/0928 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/7833

摘要： Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as amorphization and templated recrystallization (ATR) have disadvantages for fabrication of deep submicron CMOS. This invention is a method of forming an integrated circuit (IC) which has (100) and (110)-oriented regions. The method forms a directly bonded silicon (DSB) layer of (110)-oriented silicon on a (100)-oriented substrate. The DSB layer is removed in the NMOS regions and a (100)-oriented silicon layer is formed by selective epitaxial growth (SEG), using the substrate as the seed layer. NMOS transistors are formed on the SEG layer, while PMOS transistors are formed on the DSB layer. An integrated circuit formed with the inventive method is also disclosed.

摘要翻译： 在CMOS IC中的MOS晶体管中优化载流子迁移率需要为PMOS形成用于NMOS和（110）区域的（100）取向的硅区域。 诸如非晶化和模板重结晶（ATR）的方法具有制造深亚微米CMOS的缺点。 本发明是形成具有（100）和（110）取向区域的​​集成电路（IC）的方法。 该方法在（100）取向的衬底上形成（110）取向的硅的直接键合的硅（DSB）层。 在NMOS区域中去除DSB层，并且使用基底作为种子层，通过选择性外延生长（SEG）形成（100）取向硅层。 在SEG层上形成NMOS晶体管，而在DSB层上形成PMOS晶体管。 还公开了用本发明方法形成的集成电路。

公开(公告)号：US20090159933A1

公开(公告)日：2009-06-25

申请号：US12343794

申请日：2008-12-24

申请人： Angelo Pinto ,  Frank S. Johnson ,  Benjamin P. McKee ,  Shaofeng Yu

发明人： Angelo Pinto ,  Frank S. Johnson ,  Benjamin P. McKee ,  Shaofeng Yu

IPC分类号： H01L29/04 ,  H01L21/336

CPC分类号： H01L27/0928 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/7833

摘要： Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as amorphization and templated recrystallization (ATR) have disadvantages for fabrication of deep submicron CMOS. This invention is a method of forming an integrated circuit (IC) which has (100) and (110)-oriented regions. The method forms a directly bonded silicon (DSB) layer of (110)-oriented silicon on a (100)-oriented substrate. The DSB layer is removed in the NMOS regions and a (100)-oriented silicon layer is formed by selective epitaxial growth (SEG), using the substrate as the seed layer. NMOS transistors are formed on the SEG layer, while PMOS transistors are formed on the DSB layer. An integrated circuit formed with the inventive method is also disclosed.

摘要翻译： 在CMOS IC中的MOS晶体管中优化载流子迁移率需要为PMOS形成用于NMOS和（110）区域的（100）取向的硅区域。 诸如非晶化和模板重结晶（ATR）的方法具有制造深亚微米CMOS的缺点。 本发明是形成具有（100）和（110）取向区域的​​集成电路（IC）的方法。 该方法在（100）取向的衬底上形成（110）取向的硅的直接键合的硅（DSB）层。 在NMOS区域中去除DSB层，并且通过选择性外延生长（SEG），使用衬底作为种子层形成（100）取向的硅层。 在SEG层上形成NMOS晶体管，而在DSB层上形成PMOS晶体管。 还公开了用本发明方法形成的集成电路。

公开(公告)号：US20110108893A1

公开(公告)日：2011-05-12

申请号：US13007098

申请日：2011-01-14

申请人： Angelo Pinto ,  Frank S. Johnson ,  Benjamin P. McKee ,  Shaofeng Yu

发明人： Angelo Pinto ,  Frank S. Johnson ,  Benjamin P. McKee ,  Shaofeng Yu

IPC分类号： H01L27/092

CPC分类号： H01L27/0928 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/7833

摘要： Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as amorphization and templated recrystallization (ATR) have disadvantages for fabrication of deep submicron CMOS. This invention is a method of forming an integrated circuit (IC) which has (100) and (110)-oriented regions. The method forms a directly bonded silicon (DSB) layer of (110)-oriented silicon on a (100)-oriented substrate. The DSB layer is removed in the NMOS regions and a (100)-oriented silicon layer is formed by selective epitaxial growth (SEG), using the substrate as the seed layer. NMOS transistors are formed on the SEG layer, while PMOS transistors are formed on the DSB layer. An integrated circuit formed with the inventive method is also disclosed.

摘要翻译： 在CMOS IC中的MOS晶体管中优化载流子迁移率需要为PMOS形成用于NMOS和（110）区域的（100）取向的硅区域。 诸如非晶化和模板重结晶（ATR）的方法具有制造深亚微米CMOS的缺点。 本发明是形成具有（100）和（110）取向区域的​​集成电路（IC）的方法。 该方法在（100）取向的衬底上形成（110）取向的硅的直接键合的硅（DSB）层。 在NMOS区域中去除DSB层，并且使用基底作为种子层，通过选择性外延生长（SEG）形成（100）取向硅层。 在SEG层上形成NMOS晶体管，而在DSB层上形成PMOS晶体管。 还公开了用本发明方法形成的集成电路。

公开(公告)号：US07855111B2

公开(公告)日：2010-12-21

申请号：US12538048

申请日：2009-08-07

申请人： Haowen Bu ,  Shaofeng Yu ,  Angelo Pinto ,  Ajith Varghese

发明人： Haowen Bu ,  Shaofeng Yu ,  Angelo Pinto ,  Ajith Varghese

IPC分类号： H01L21/8238 ,  H01L27/118

CPC分类号： H01L21/26506 ,  H01L21/187 ,  H01L21/324 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/045 ,  H01L29/665

摘要： Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS transistors. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells. This invention provides a method of forming a HOT substrate containing regions with two different silicon crystal lattice orientations, with boundary morphology less than 40 nanometers wide. Starting with a direct silicon bonded (DSB) wafer of a (100) substrate wafer and a (110) DBS layer, NMOS regions in the DSB layer are amorphized by a double implant and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Crystal defects during anneal are prevented by a low temperature oxide layer on the top surface of the wafer. An integrated circuit formed with the inventive method is also disclosed.

摘要翻译： 用于CMOS IC的混合取向技术（HOT）衬底包括用于NMOS的（100）取向硅区域和用于优化各个MOS晶体管中的载流子迁移率的用于PMOS的（110）区域。 （100）和（110）区域之间的边界区域必须足够窄以支持高栅极密度和SRAM单元。 本发明提供一种形成含有两个不同硅晶格取向的区域的HOT衬底的方法，边界形貌小于40纳米宽。 从（100）衬底晶片和（110）DBS层的直接硅键合（DSB）晶片开始，DSB层中的NMOS区域被双注入物非晶化，并通过固相外延（100）取向（100）取向重结晶 SPE）。 退火期间的晶体缺陷通过晶片顶表面上的低温氧化物层来防止。 还公开了用本发明方法形成的集成电路。

公开(公告)号：US20100032727A1

公开(公告)日：2010-02-11

申请号：US12538048

申请日：2009-08-07

申请人： Haowen Bu ,  Shaofeng Yu ,  Angelo Pinto ,  Ajith Varghese

发明人： Haowen Bu ,  Shaofeng Yu ,  Angelo Pinto ,  Ajith Varghese

IPC分类号： H01L27/092 ,  H01L21/20 ,  H01L21/8238

CPC分类号： H01L21/26506 ,  H01L21/187 ,  H01L21/324 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/045 ,  H01L29/665

摘要： Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS transistors. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells. This invention provides a method of forming a HOT substrate containing regions with two different silicon crystal lattice orientations, with boundary morphology less than 40 nanometers wide. Starting with a direct silicon bonded (DSB) wafer of a (100) substrate wafer and a (110) DBS layer, NMOS regions in the DSB layer are amorphized by a double implant and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Crystal defects during anneal are prevented by a low temperature oxide layer on the top surface of the wafer. An integrated circuit formed with the inventive method is also disclosed.

摘要翻译： 用于CMOS IC的混合取向技术（HOT）衬底包括用于NMOS的（100）取向硅区域和用于优化各个MOS晶体管中的载流子迁移率的用于PMOS的（110）区域。 （100）和（110）区域之间的边界区域必须足够窄以支持高栅极密度和SRAM单元。 本发明提供一种形成含有两个不同硅晶格取向的区域的HOT衬底的方法，边界形貌小于40纳米宽。 从（100）衬底晶片和（110）DBS层的直接硅键合（DSB）晶片开始，DSB层中的NMOS区域被双注入物非晶化，并通过固相外延（100）取向（100）取向重结晶 SPE）。 退火期间的晶体缺陷通过晶片顶表面上的低温氧化物层来防止。 还公开了用本发明方法形成的集成电路。

公开(公告)号：US20110180881A1

公开(公告)日：2011-07-28

申请号：US13082129

申请日：2011-04-07

申请人： Angelo Pinto ,  Frank S. Johnson

发明人： Angelo Pinto ,  Frank S. Johnson

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/187 ,  H01L29/045 ,  H01L29/665

摘要： Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells appropriate for the technology node. This invention provides a method of forming an integrated circuit (IC) substrate containing regions with two different silicon crystal lattice orientations. Starting with a (110) direct silicon bonded (DSB) layer on a (100) substrate, regions in the DSB layer are amorphized and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Lateral templating by the DSB layer is reduced by amorphization of the upper portion of the (110) regions through a partially absorbing amorphization hard mask. Boundary morphology is less than 40 nanometers wide. An integrated circuit formed with the inventive method is also disclosed.

摘要翻译： 在CMOS IC中的MOS晶体管中优化载流子迁移率需要为PMOS形成用于NMOS和（110）区域的（100）取向的硅区域。 （100）和（110）区域之间的边界区域必须足够窄以支持适合于技术节点的高栅极密度和SRAM单元。 本发明提供一种形成含有具有两个不同硅晶格取向的区域的集成电路（IC）基板的方法。 从（100）衬底上的（110）直接硅键合（DSB）层开始，DSB层中的区域通过固相外延（SPE）在（100）取向上非晶化并重结晶。 DSB层的侧向模板通过部分吸收的非晶化硬掩模使（110）区域的上部非晶化而减少。 边界形态小于40纳米宽。 还公开了用本发明方法形成的集成电路。

公开(公告)号：US20090159932A1

公开(公告)日：2009-06-25

申请号：US12343743

申请日：2008-12-24

申请人： Angelo Pinto ,  Frank S. Johnson

发明人： Angelo Pinto ,  Frank S. Johnson

IPC分类号： H01L29/04 ,  H01L21/20 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/187 ,  H01L29/045 ,  H01L29/665

摘要： Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells appropriate for the technology node. This invention provides a method of forming an integrated circuit (IC) substrate containing regions with two different silicon crystal lattice orientations. Starting with a (110) direct silicon bonded (DSB) layer on a (100) substrate, regions in the DSB layer are amorphized and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Lateral templating by the DSB layer is reduced by amorphization of the upper portion of the (110) regions through a partially absorbing amorphization hard mask. Boundary morphology is less than 40 nanometers wide. An integrated circuit formed with the inventive method is also disclosed.

摘要翻译： 在CMOS IC中的MOS晶体管中优化载流子迁移率需要为PMOS形成用于NMOS和（110）区域的（100）取向的硅区域。 （100）和（110）区域之间的边界区域必须足够窄以支持适合于技术节点的高栅极密度和SRAM单元。 本发明提供一种形成含有具有两个不同硅晶格取向的区域的集成电路（IC）基板的方法。 从（100）衬底上的（110）直接硅键合（DSB）层开始，DSB层中的区域通过固相外延（SPE）在（100）取向上非晶化并重结晶。 DSB层的侧向模板通过部分吸收的非晶化硬掩模使（110）区域的上部非晶化而减少。 边界形态小于40纳米宽。 还公开了用本发明方法形成的集成电路。

公开(公告)号：US07943451B2

公开(公告)日：2011-05-17

申请号：US12343743

申请日：2008-12-24

申请人： Angelo Pinto ,  Frank S. Johnson

发明人： Angelo Pinto ,  Frank S. Johnson

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/187 ,  H01L29/045 ,  H01L29/665

摘要： Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells appropriate for the technology node. This invention provides a method of forming an integrated circuit (IC) substrate containing regions with two different silicon crystal lattice orientations. Starting with a (110) direct silicon bonded (DSB) layer on a (100) substrate, regions in the DSB layer are amorphized and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Lateral templating by the DSB layer is reduced by amorphization of the upper portion of the (110) regions through a partially absorbing amorphization hard mask. Boundary morphology is less than 40 nanometers wide. An integrated circuit formed with the inventive method is also disclosed.

摘要翻译： 在CMOS IC中的MOS晶体管中优化载流子迁移率需要为PMOS形成用于NMOS和（110）区域的（100）取向的硅区域。 （100）和（110）区域之间的边界区域必须足够窄以支持适合于技术节点的高栅极密度和SRAM单元。 本发明提供一种形成含有具有两个不同硅晶格取向的区域的集成电路（IC）基板的方法。 从（100）衬底上的（110）直接硅键合（DSB）层开始，DSB层中的区域通过固相外延（SPE）在（100）取向上非晶化并重结晶。 DSB层的侧向模板通过部分吸收的非晶化硬掩模使（110）区域的上部非晶化而减少。 边界形态小于40纳米宽。 还公开了用本发明方法形成的集成电路。

公开(公告)号：US08043947B2

公开(公告)日：2011-10-25

申请号：US11941187

申请日：2007-11-16

申请人： Angelo Pinto ,  Weize Xiong ,  Manfred Ramin

发明人： Angelo Pinto ,  Weize Xiong ,  Manfred Ramin

IPC分类号： H01L21/425

CPC分类号： H01L21/187 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02667 ,  H01L21/76224

摘要： A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation, a second crystal orientation, and a border region disposed between the first and second crystal orientations. The border region further has a defect associated with an interface of the first crystal orientation and second the second crystal orientation, wherein the defect generally extends a distance into the semiconductor body from a surface of the body. A sacrificial portion of the semiconductor body is removed from the surface thereof, wherein removing the sacrificial portion at least partially removes the defect. The sacrificial portion can be defined by oxidizing the surface at low temperature, wherein the oxidation at least partially consumes the defect. The sacrificial portion can also be removed by CMP. An STI feature may be further formed over the defect after removal of the sacrificial portion, therein consuming any remaining defect.

摘要翻译： 一种用于半导体处理的方法提供了具有第一晶体取向，第二晶体取向和设置在第一和第二晶体取向之间的边界区域的DSB半导体本体。 边界区域还具有与第一晶体取向和第二晶体取向的界面相关联的缺陷，其中缺陷通常从身体的表面延伸到半导体本体中的距离。 从其表面去除半导体本体的牺牲部分，其中去除牺牲部分至少部分地去除缺陷。 牺牲部分可以通过在低温下氧化表面来限定，其中氧化至少部分地消耗缺陷。 牺牲部分也可以通过CMP去除。 在去除牺牲部分之后，可以在缺陷上进一步形成STI特征，其中消耗任何剩余的缺陷。