Digital signal processing block having a wide multiplexer
    6.
    发明授权
    Digital signal processing block having a wide multiplexer 有权
    具有宽多路复用器的数字信号处理块

    公开(公告)号:US07865542B2

    公开(公告)日:2011-01-04

    申请号:US11433120

    申请日:2006-05-12

    IPC分类号: G06F7/38

    摘要: A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.

    摘要翻译: 一种数字信号处理块,具有:1)第一数字信号处理元件,包括:第一多路复用器的第一多路复用器,所述第一多路复用器在第一数据输入和第一零常数输入之间进行选择; 以及耦合到所述第一多个复用器的第一算术单元,所述第一算术逻辑单元被配置为用于相加; 以及2)第二数字信号处理元件,包括:第二多路复用器的第二多路复用器,所述第二多路复用器在第二数据输入和第二零常数输入之间进行选择; 以及耦合到所述第二多路复用器的第二运算单元和所述第一多路复用器的第三多路复用器,所述第二运算单元被配置为相加。