公开(公告)号：US08407652B2

公开(公告)日：2013-03-26

申请号：US12972879

申请日：2010-12-20

申请人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan ,  Brian C. Wilson

发明人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan ,  Brian C. Wilson

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful.

摘要翻译： 基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。 来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象 变革的表现已经取得成功。 然后，子进程通知那些符合候选对象的那些对象的父进程，以便父进程只需对候选对象执行转换，从而将父进程从与非候选对象执行转换相关的开销中解除 子进程已将该转换确定为未成功的对象。

公开(公告)号：US20120159417A1

公开(公告)日：2012-06-21

申请号：US12972879

申请日：2010-12-20

申请人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan ,  Brian C. Wilson

发明人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan ,  Brian C. Wilson

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful.

摘要翻译： 基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。 来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象 变革的表现已经取得成功。 然后，子进程通知那些符合候选对象的那些对象的父进程，以便父进程只需对候选对象执行转换，从而将父进程从与非候选对象执行转换相关的开销中解除 子进程已将该转换确定为未成功的对象。

公开(公告)号：US20120159406A1

公开(公告)日：2012-06-21

申请号：US12972980

申请日：2010-12-20

申请人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan

发明人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A task-based multi-process design synthesis methodology is reproducible, and relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also undoes the transform performed for each object such that the same initial state of the integrated circuit design is used to perform each transform. In addition, the parent process tracks the results of performing the transform by each child process, and applies successful transforms in a controlled sequence.

摘要翻译： 基于任务的多进程设计合成方法是可重复的，并且依赖于多个子进程来辅助父进程对集成电路设计进行优化。 来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象 变革的表现已经取得成功。 每个子进程还撤消对每个对象执行的变换，使得集成电路设计的相同初始状态被用于执行每个变换。 此外，父进程跟踪每个子进程执行变换的结果，并以受控序列应用成功的转换。

公开(公告)号：US08341565B2

公开(公告)日：2012-12-25

申请号：US12972980

申请日：2010-12-20

申请人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan

发明人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A task-based multi-process design synthesis methodology is reproducible, and relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also undoes the transform performed for each object such that the same initial state of the integrated circuit design is used to perform each transform. In addition, the parent process tracks the results of performing the transform by each child process, and applies successful transforms in a controlled sequence.

摘要翻译： 基于任务的多进程设计合成方法是可重复的，并且依赖于多个子进程来辅助父进程对集成电路设计进行优化。 来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象 变革的表现已经取得成功。 每个子进程还撤消对每个对象执行的变换，使得集成电路设计的相同初始状态被用于执行每个变换。 此外，父进程跟踪每个子进程执行变换的结果，并以受控序列应用成功的转换。

公开(公告)号：US08584070B2

公开(公告)日：2013-11-12

申请号：US13252868

申请日：2011-10-04

申请人： Charles J. Alpert ,  Zhuo Li ,  Lakshmi N. Reddy ,  Chin Ngai Sze ,  Yaoguang Wei

发明人： Charles J. Alpert ,  Zhuo Li ,  Lakshmi N. Reddy ,  Chin Ngai Sze ,  Yaoguang Wei

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Global routing congestion in an integrated circuit design is characterized by computing global edge congestions and constructing a histogram of averages of the global edge congestions for varying percentages of worst edge congestion, e.g., 0.5%, 1%, 2%, 5%, 10% and 20%. Horizontal and vertical global edges are handled separately. Global edges near blockages can be skipped to avoid false congestion hotspots. The histogram of the current global routing can be compared to a histogram for a previous global routing to select a best routing solution. The histograms can also be used in conjunction with congestion-driven physical synthesis tools.

摘要翻译： 集成电路设计中的全局路由拥塞的特征在于计算全局边缘拥塞并构建全局边缘拥塞的平均值的直方图，用于不同百分比的最差边缘拥塞，例如0.5％，1％，2％，5％，10％ 和20％。 水平和垂直的全局边缘分开处理。 可以跳过阻塞附近的全局边缘，以避免虚假拥塞热点。 可将当前全局路由的直方图与先前全局路由的直方图进行比较，以选择最佳路由解决方案。 直方图还可以与拥塞驱动的物理综合工具结合使用。

公开(公告)号：US08495534B2

公开(公告)日：2013-07-23

申请号：US12796550

申请日：2010-06-08

申请人： Charles J. Alpert ,  Zhuo D. Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi N. Reddy ,  Jarrod A. Roy ,  Taraneh E. Taghavi ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Zhuo D. Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi N. Reddy ,  Jarrod A. Roy ,  Taraneh E. Taghavi ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.

摘要翻译： 一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。 扩展器将单元格分配给图块。 扩展器确定高度详细的路由成本瓦片类，其中高详细路由成本瓦片类是具有高详细路由成本的一类瓦片。 扩展器选择高详细路由代价块类别的块内的单元，以在所选择的块中形成选定的单元。 扩展器应用多种技术在新位置重新定位这些单元，以提高详细的可布线性。 扩展器可以在所选择的单元周围放置扩展的边界框，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片，并且在边界框内重新定位所选择的单元以形成修改的设计以改进详细的可布线性。 扩张器也可能使这些细胞膨胀并合法化。

公开(公告)号：US20130086545A1

公开(公告)日：2013-04-04

申请号：US13252868

申请日：2011-10-04

申请人： Charles J. Alpert ,  Zhuo Li ,  Lakshmi N. Reddy ,  Chin Ngai Sze ,  Yaoguang Wei

发明人： Charles J. Alpert ,  Zhuo Li ,  Lakshmi N. Reddy ,  Chin Ngai Sze ,  Yaoguang Wei

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Global routing congestion in an integrated circuit design is characterized by computing global edge congestions and constructing a histogram of averages of the global edge congestions for varying percentages of worst edge congestion, e.g., 0.5%, 1%, 2%, 5%, 10% and 20%. Horizontal and vertical global edges are handled separately. Global edges near blockages can be skipped to avoid false congestion hotspots. The histogram of the current global routing can be compared to a histogram for a previous global routing to select a best routing solution. The histograms can also be used in conjunction with congestion-driven physical synthesis tools.

摘要翻译： 集成电路设计中的全局路由拥塞的特征在于计算全局边缘拥塞并构建全局边缘拥塞的平均值的直方图，用于不同百分比的最差边缘拥塞，例如0.5％，1％，2％，5％，10％ 和20％。 水平和垂直的全局边缘分开处理。 可以跳过阻塞附近的全局边缘，以避免虚假拥塞热点。 可将当前全局路由的直方图与先前全局路由的直方图进行比较，以选择最佳路由解决方案。 直方图还可以与拥塞驱动的物理综合工具结合使用。

公开(公告)号：US20110302544A1

公开(公告)日：2011-12-08

申请号：US12796550

申请日：2010-06-08

申请人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi N. Reddy ,  Jarrod A. Roy ,  Taraneh Taghavi ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi N. Reddy ,  Jarrod A. Roy ,  Taraneh Taghavi ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.

摘要翻译： 一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。 扩展器将单元格分配给图块。 扩展器确定高度详细的路由成本瓦片类，其中高详细路由成本瓦片类是具有高详细路由成本的一类瓦片。 扩展器选择高详细路由代价块类别的块内的单元，以在所选择的块中形成选定的单元。 扩展器应用多种技术在新位置重新定位这些单元，以提高详细的可布线性。 扩展器可以在所选择的单元周围放置扩展的边界框，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片，并且在边界框内重新定位所选择的单元以形成修改的设计以改进详细的可布线性。 扩张器也可能使这些细胞膨胀并合法化。