公开(公告)号：US20120159406A1

公开(公告)日：2012-06-21

申请号：US12972980

申请日：2010-12-20

申请人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan

发明人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A task-based multi-process design synthesis methodology is reproducible, and relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also undoes the transform performed for each object such that the same initial state of the integrated circuit design is used to perform each transform. In addition, the parent process tracks the results of performing the transform by each child process, and applies successful transforms in a controlled sequence.

摘要翻译： 基于任务的多进程设计合成方法是可重复的，并且依赖于多个子进程来辅助父进程对集成电路设计进行优化。 来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象 变革的表现已经取得成功。 每个子进程还撤消对每个对象执行的变换，使得集成电路设计的相同初始状态被用于执行每个变换。 此外，父进程跟踪每个子进程执行变换的结果，并以受控序列应用成功的转换。

公开(公告)号：US08407652B2

公开(公告)日：2013-03-26

申请号：US12972879

申请日：2010-12-20

申请人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan ,  Brian C. Wilson

发明人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan ,  Brian C. Wilson

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful.

摘要翻译： 基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。 来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象 变革的表现已经取得成功。 然后，子进程通知那些符合候选对象的那些对象的父进程，以便父进程只需对候选对象执行转换，从而将父进程从与非候选对象执行转换相关的开销中解除 子进程已将该转换确定为未成功的对象。

公开(公告)号：US08341565B2

公开(公告)日：2012-12-25

申请号：US12972980

申请日：2010-12-20

申请人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan

发明人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A task-based multi-process design synthesis methodology is reproducible, and relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also undoes the transform performed for each object such that the same initial state of the integrated circuit design is used to perform each transform. In addition, the parent process tracks the results of performing the transform by each child process, and applies successful transforms in a controlled sequence.

摘要翻译： 基于任务的多进程设计合成方法是可重复的，并且依赖于多个子进程来辅助父进程对集成电路设计进行优化。 来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象 变革的表现已经取得成功。 每个子进程还撤消对每个对象执行的变换，使得集成电路设计的相同初始状态被用于执行每个变换。 此外，父进程跟踪每个子进程执行变换的结果，并以受控序列应用成功的转换。

公开(公告)号：US20120159417A1

公开(公告)日：2012-06-21

申请号：US12972879

申请日：2010-12-20

申请人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan ,  Brian C. Wilson

发明人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan ,  Brian C. Wilson

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful.

摘要翻译： 基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。 来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象 变革的表现已经取得成功。 然后，子进程通知那些符合候选对象的那些对象的父进程，以便父进程只需对候选对象执行转换，从而将父进程从与非候选对象执行转换相关的开销中解除 子进程已将该转换确定为未成功的对象。

公开(公告)号：US20120159418A1

公开(公告)日：2012-06-21

申请号：US12972934

申请日：2010-12-20

申请人： Anthony D. Drumm ,  Frank J. Musante ,  Jagannathan Narasimhan ,  Louise H. Trevillyan

发明人： Anthony D. Drumm ,  Frank J. Musante ,  Jagannathan Narasimhan ,  Louise H. Trevillyan

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also provides result data to the parent process for each candidate object to reduce the overhead of the parent process when performing the transform on the candidate object. The result data, which may include, for example, a set of instructions or hints, may allow a parent process to take advantage of the efforts of the child process in performing the transform.

摘要翻译： 基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。 来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象 变革的表现已经取得成功。 每个子进程还将结果数据提供给每个候选对象的父进程，以便在对候选对象执行变换时减少父进程的开销。 可以包括例如一组指令或提示的结果数据可以允许父进程利用子进程执行变换的努力。

公开(公告)号：US08392866B2

公开(公告)日：2013-03-05

申请号：US12972934

申请日：2010-12-20

申请人： Anthony D. Drumm ,  Frank J. Musante ,  Jagannathan Narasimhan ,  Louise H. Trevillyan

发明人： Anthony D. Drumm ,  Frank J. Musante ,  Jagannathan Narasimhan ,  Louise H. Trevillyan

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also provides result data to the parent process for each candidate object to reduce the overhead of the parent process when performing the transform on the candidate object. The result data, which may include, for example, a set of instructions or hints, may allow a parent process to take advantage of the efforts of the child process in performing the transform.

摘要翻译： 基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。 来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象 变革的表现已经取得成功。 每个子进程还将结果数据提供给每个候选对象的父进程，以便在对候选对象执行变换时减少父进程的开销。 可以包括例如一组指令或提示的结果数据可以允许父进程利用子进程执行变换的努力。

公开(公告)号：US20120054699A1

公开(公告)日：2012-03-01

申请号：US12868086

申请日：2010-08-25

申请人： Minsik Cho ,  Victor N. Kravets ,  Smita Krishnaswamy ,  Dorothy Kucar ,  Jagannathan Narasimhan ,  Ruchir Puri ,  Haifeng Qian ,  Haoxing Ren ,  Chin Ngai Sze ,  Louise H. Trevillyan ,  Hua Xiang ,  Matthew M. Ziegler

发明人： Minsik Cho ,  Victor N. Kravets ,  Smita Krishnaswamy ,  Dorothy Kucar ,  Jagannathan Narasimhan ,  Ruchir Puri ,  Haifeng Qian ,  Haoxing Ren ,  Chin Ngai Sze ,  Louise H. Trevillyan ,  Hua Xiang ,  Matthew M. Ziegler

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.

摘要翻译： 示例性实施例包括用于大块和结构化合成的计算机实现的方法，所述方法包括从合成流的起点确定初始设计数据，接收用户导向的结构化被并入到合成流中，对初始设计数据应用逻辑合成， 对初始设计数据应用物理设计，确定电路设计参数是否已满足，并响应于电路设计参数不满足，调整电路设计参数。

公开(公告)号：US08271920B2

公开(公告)日：2012-09-18

申请号：US12868086

申请日：2010-08-25

申请人： Minsik Cho ,  Victor N. Kravets ,  Smita Krishnaswamy ,  Dorothy Kucar ,  Jagannathan Narasimhan ,  Ruchir Puri ,  Haifeng Qian ,  Haoxing Ren ,  Chin Ngai Sze ,  Louise H. Trevillyan ,  Hua Xiang ,  Matthew M. Ziegler

发明人： Minsik Cho ,  Victor N. Kravets ,  Smita Krishnaswamy ,  Dorothy Kucar ,  Jagannathan Narasimhan ,  Ruchir Puri ,  Haifeng Qian ,  Haoxing Ren ,  Chin Ngai Sze ,  Louise H. Trevillyan ,  Hua Xiang ,  Matthew M. Ziegler

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.

摘要翻译： 示例性实施例包括用于大块和结构化合成的计算机实现的方法，所述方法包括从合成流的起点确定初始设计数据，接收用户导向的结构化被并入到合成流中，对初始设计数据应用逻辑合成， 对初始设计数据应用物理设计，确定电路设计参数是否已满足，并响应于电路设计参数不满足，调整电路设计参数。

公开(公告)号：US20090217227A1

公开(公告)日：2009-08-27

申请号：US12035950

申请日：2008-02-22

申请人： MICHAEL W. DOTSON ,  Anthony DeGroff Drumm ,  Dazhuang J. Ma ,  Ruchir Puri ,  Louise H. Trevillyan

发明人： MICHAEL W. DOTSON ,  Anthony DeGroff Drumm ,  Dazhuang J. Ma ,  Ruchir Puri ,  Louise H. Trevillyan

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.

摘要翻译： 在一个实施例中，本发明是用于半导体芯片设计的并行处理的方法和装置。 用于处理半导体芯片设计的方法的一个实施例包括平坦化对应于半导体芯片设计的网表，对并入在扁平化网表中的一个或多个逻辑元件执行逻辑聚类以生成一个或多个簇，根据该划分半导体芯片设计 使用一个或多个集群，并且并行设计各个分区。

公开(公告)号：US20090019415A1

公开(公告)日：2009-01-15

申请号：US12237246

申请日：2008-09-24

申请人： Mark A. Lavin ,  Ruchir Puri ,  Louise H. Trevillyan ,  Hua Xiang

发明人： Mark A. Lavin ,  Ruchir Puri ,  Louise H. Trevillyan ,  Hua Xiang

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.

摘要翻译： 本发明提供了一种用于在芯片的设计阶段减轻互连变化的影响的方法，系统和程序产品。 在本发明的技术下，确定了芯片互连的全局和详细路由。 此后，执行虚拟填充估计和网格基金属密度估计。 然后，基于CMP模型，获得金属厚度的可变图。 基于可变图，识别对金属变化敏感的芯片的接线网（例如，由于CMP过程中的金属厚度损失/增益而不能满足定时闭合）。 然后将这些接线网重新布线以优化芯片。