公开(公告)号：US5241450A

公开(公告)日：1993-08-31

申请号：US850642

申请日：1992-03-13

申请人： Anthony F. Bernhardt ,  Robert W. Petersen

发明人： Anthony F. Bernhardt ,  Robert W. Petersen

IPC分类号： H01L25/00 ,  H01L23/473 ,  H01L23/52 ,  H01L23/538 ,  H01L25/10 ,  H05K7/02

CPC分类号： H01L23/473 ,  H01L23/5385 ,  H01L24/24 ,  H05K7/023 ,  H01L25/105 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/1627 ,  H01L2924/3011 ,  H01L2924/3511

摘要： A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow "dummy chips" are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned o the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.

摘要翻译： 多个多芯片模块通过销售凸块连接到例如周边的三个侧面上的相邻模块而堆叠并围绕周边粘合。 根据芯片组的特定设计考虑，第四面可以用于冷却剂分配，更多互连结构或其他特征。 多芯片模块包括具有形成在第一主表面上的平坦化互连结构的电路板和结合到平坦化互连表面的集成电路芯片。 在每个电路板的周围，长而窄的“虚拟芯片”被结合到成品电路板上以形成周边壁。 墙壁高于电路板上的任何芯片，使得上述板的平坦背面仅接触周边壁。 模块到模块互连以相同的方式在板的侧面和周边壁上被激光图案化，并且同时该芯片对板互连可以是激光图案化的。

公开(公告)号：US6034438A

公开(公告)日：2000-03-07

申请号：US733854

申请日：1996-10-18

申请人： Robert W. Petersen

发明人： Robert W. Petersen

IPC分类号： H01L25/065 ,  H05K3/36 ,  H01L29/04

CPC分类号： H01L25/0657 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2924/0002

摘要： Integrated circuit chips and method of routing the interface pads from the face of the chip or die to one or more sidewall surfaces of the die. The interconnection is routed from the face of the die to one or more edges of the die, then routed over the edge of the die and onto the side surface. A new pad is then formed on the sidewall surface, which allows multiple die or chips to be stacked in a three-dimensional array, while enabling follow-on signal routing from the sidewall pads. The routing of the interconnects and formation of the sidewall pads can be carried out in an L-connect or L-shaped routing configuration, using a metalization process such as laser pantography.

摘要翻译： 集成电路芯片和将接口焊盘从芯片或管芯的表面路由到管芯的一个或多个侧壁表面的方法。 互连从管芯的表面被引导到管芯的一个或多个边缘，然后在管芯的边缘上被引导到侧面上。 然后在侧壁表面上形成新的焊盘，这允许多个管芯或芯片以三维阵列堆叠，同时实现从侧壁焊盘的后续信号路由。 互连的路由和侧壁焊盘的形成可以使用诸如激光缩放的金属化处理以L连接或L形路由配置来执行。