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1.发明授权Global wire management apparatus and method for a multiple-port random access memory 失效用于多端口随机存取存储器的全局线路管理装置和方法
公开(公告)号：US5991224A
公开(公告)日：1999-11-23
申请号：US84127
申请日：1998-05-22
摘要： A global wire management apparatus and method for a multiple port random access memory (RAM) is disclosed. The RAM includes an array of stacked dual memory cell structures each including a common row/column decoder disposed between an upper memory cell and lower memory cell. The upper memory cell is situated adjacent upper transfer gate circuitry, and the lower memory cell is situated adjacent lower transfer gate circuitry. The decoder circuit is oriented vertically in the middle of the dual memory cell structure so that the true and complement decoder outputs may be fed upwards and downwards to the upper and lower transfer gate circuits. Wiring of the upper and lower transfer gate circuits may be effected completely at the local interconnect layer. Each of the write ports of the common decoder includes a NAND gate, an inverter, and a transfer gate for each of the upper and lower memory cells for controlling the transfer of data to the upper and lower memory cells. The disclosed global wiring management methodology provides an approach for reducing the number of global interconnect wires in a multiple port random access memory cell by sharing various wiring channels between memory cells. Such an approach allows a number of the memory cell global signal interconnects to be moved from the global wiring plane to the local wiring plane.
摘要翻译： 公开了一种用于多端口随机存取存储器（RAM）的全局线管理装置和方法。 RAM包括堆叠的双存储器单元结构的阵列，每个阵列包括布置在上部存储器单元和下部存储器单元之间的公共行/列解码器。 上存储器单元位于上传输门电路附近，并且下存储器单元位于下传输门电路附近。 解码器电路在双存储单元结构的中间垂直取向，使得真和补码解码器输出可以向上和向下馈送到上传输门电路和下传输门电路。 上部和下部传输门电路的接线可以在局部互连层完全实现。 公共解码器的每个写入端口包括用于控制向上部和下部存储器单元传输数据的上部和下部存储器单元中的每一个的“与非”门，反相器和传输门。 所公开的全局布线管理方法提供了一种通过在存储器单元之间共享各种布线通道来减少多端口随机存取存储单元中的全局互连线数量的方法。 这种方法允许多个存储单元全局信号互连从全局布线平面移动到局部布线平面。
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2.发明授权Write multiplexer apparatus and method for multiple write port programmable memory 失效用于多写入端口可编程存储器的多路复用器装置和方法
公开(公告)号：US5991208A
公开(公告)日：1999-11-23
申请号：US084134
申请日：1998-05-22
CPC分类号： G11C8/16
摘要： An improved apparatus and method for facilitating multiple write port access to a programmable memory apparatus is disclosed. A memory array, such as a random access memory array, includes a plurality of memory cells. A number of write ports are coupled to the memory array, each of which provides write access to individual memory cells of the memory array. Each of the write ports includes a NAND gate, an inverter, and a transfer gate. The NAND gate includes first and second inputs respectively coupled to a write row select line and a write column select line, and an output coupled to the input of the inverter and a first control input of the transfer gate. The output of the inverter is coupled to a second control input of the transfer gate. The input of the transfer gate is coupled to a data line, and the output of the transfer gate is coupled to a memory cell of the memory array. In response to appropriate logic levels on the write row select line and write column select line, data on the data input line is transferred through the transfer gate and written into the memory cell. Reduced node capacitance at the input of the memory cell and an increase in memory cell write speed are realized by implementing the disclosed write port circuitry.
摘要翻译： 公开了一种用于促进对可编程存储装置的多个写入口访问的改进的装置和方法。 诸如随机存取存储器阵列的存储器阵列包括多个存储器单元。 多个写入端口耦合到存储器阵列，每个写入端口提供对存储器阵列的各个存储器单元的写访问。 每个写入端口包括NAND门，反相器和传输门。 NAND门包括分别耦合到写入行选择线和写入列选择线的第一和第二输入，以及耦合到反相器的输入和传输门的第一控制输入的输出。 反相器的输出耦合到传输门的第二控制输入端。 传输门的输入耦合到数据线，并且传输门的输出耦合到存储器阵列的存储单元。 响应于写行选择线和写列选择线上的适当逻辑电平，数据输入线上的数据通过传输门传输并写入存储单元。 通过实现所公开的写入端口电路来实现在存储器单元输入端减少的节点电容和存储单元写入速度的增加。
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3.发明授权Method and apparatus for prioritizing and routing commands from a command source to a command sink 失效从命令源到命令宿优先级和路由命令的方法和装置
公开(公告)号：US6000012A
公开(公告)日：1999-12-07
申请号：US761380
申请日：1996-12-09
CPC分类号： G06F12/0897
摘要： A method and apparatus for prioritizing and routing commands from a command source to a command sink. The command directory receives and stores a command from at least one command source. The data buffer stores the data associated with the command in the allocated portion of the data buffer. Based on status information also stored by the command directory with respect to each command, routing logic in the command directory, corresponding to each command sink, identifies which commands stored in the command buffer to route to the command sink, and routes the identified commands to the command sink. The routing logic also determines a priority of the identified commands and routes the identified commands in order of priority.
摘要翻译： 一种用于从命令源到命令接收器的优先级和路由命令的方法和装置。 命令目录接收并存储至少一个命令源的命令。 数据缓冲器将与命令相关联的数据存储在数据缓冲器的分配部分中。 根据命令目录相对于每个命令存储的状态信息，命令目录中对应于每个命令宿的路由逻辑识别存储在命令缓冲器中的哪些命令路由到命令宿，并将所识别的命令路由到 命令槽。 路由逻辑还确定所识别的命令的优先级，并且以优先级顺序路由所识别的命令。
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公开(公告)号：US5748919A
公开(公告)日：1998-05-05
申请号：US677775
申请日：1996-07-10
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
CPC分类号： G06F13/4018
摘要： A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.
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公开(公告)号：US06523080B1
公开(公告)日：2003-02-18
申请号：US09014090
申请日：1998-01-27
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
IPC分类号： G06F1342
CPC分类号： G06F13/385
摘要： A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.
摘要翻译： 提供共享总线非顺序数据排序方法和装置。 识别最大总线宽度值和最小传输值。 响应于所识别的最大总线宽度值和最小传输值来识别最小数量的子传送。 具有用于接收和/或发送数据的最大数量的码片的总线单元在多个子传送期间以预定义的顺序接收数据。 在每个数据子传送期间，相应的预定义字被传送到总线单元的每个芯片。
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公开(公告)号：US6035424A
公开(公告)日：2000-03-07
申请号：US761379
申请日：1996-12-09
CPC分类号： G06F12/0897
摘要： An apparatus for tracking processing of commands between command sources and sinks includes a command directory. The command directory receives a command from at least one command source, receives signals from command sinks, generates status information corresponding to the command based on the command and the received signals, and stores the status information. The status information indicates to which command sink the command is to be routed, whether the command sink has accepted the command, and whether the command sink has completed processing the command. The command directory includes a command buffer having a plurality of directory entries. The command buffer stores a command and associated status information in a directory entry. The command buffer also includes free buffer logic which monitors the status information in each directory entry. Based on this monitoring, the free buffer logic determines whether a directory entry has been disabled or whether command tracking errors exist.
摘要翻译： 用于跟踪命令源和接收器之间的命令处理的装置包括命令目录。 命令目录从至少一个命令源接收命令，从命令接收器接收信号，根据命令和接收到的信号生成与命令对应的状态信息，并存储状态信息。 状态信息表示命令接收命令将被路由到哪个命令宿，命令宿是否已接受命令，以及命令宿是否已完成处理命令。 命令目录包括具有多个目录条目的命令缓冲器。 命令缓冲区将命令和关联的状态信息存储在目录条目中。 命令缓冲区还包括可用的缓冲逻辑，它监视每个目录条目中的状态信息。 基于该监视，可用缓冲器逻辑确定目录条目是否被禁用或者是否存在命令跟踪错误。
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