Abstract:
A hierarchical display of protocol layers for communication data. Fields of the communication data are converted into field cells where each field cell has a text field and a field descriptor. The field cells for each protocol layer are arranged by an interpreter into protocol units according to a protocol standard for that layer and then displayed in a hierarchical manner. Detailed specifications for field cells taken directly from the protocol standard can be displayed by using a cursor over the field cell. Indicators in particular ones of the field cells allow certain field cells within a protocol unit to be collapsed or expanded within the protocol unit or allow lower protocol units to be collapsed or expanded into the higher protocol units.
Abstract:
A multi-port Fibre Channel controller is disclosed. Such a multi-port Fibre Channel controller includes a number of Fibre Channel ports, an interface unit coupled to each one of the Fibre Channel ports, a Fibre Channel controller, and a processor. The processor is coupled to the Fibre Channel controller, and the Fibre Channel controller is coupled to control the interface unit and coupled to the subsystem interface. Such a multi-port Fibre Channel controller may be configured as a dual-port Fibre Channel controller by, for example, employing only two Fibre Channel ports (i.e., a first Fibre Channel port and a second Fibre Channel port).
Abstract:
Split IEEE 1394 bridges utilize individual portals or bundles of portals to communicate over a non-full-featured IEEE 1394 network such as a local or wide area network in combination with IEEE 1394 multi-portal bridges. Multi-portal bridges may be formed through the connection of several split bridges each with one or more IEEE 1394 portals over a core net. The core net is invisible to the IEEE 1394 nodes with respect to traffic originating from an IEEE 1394 bus for a destination in an IEEE 1394 bus, and the network elements allow for increased network scalability in both terms of physical size and levels of hierarchy. Useful properties of a core net such as availability of high-performance switches or increased reach are incorporated into an IEEE 1394 network.
Abstract:
A bus bandwidth consumption profiler for measuring and reporting bus cycle utilization in a system having multiple bus masters, including master counters paired with the masters to count cycles of bus ownership, and a realtime counter to count elapsed cycles between profile events generated by either a realtime counter roll-over, or a system read signal. Upon a profile event, the counts of the master counters are simultaneously output to the system and the realtime count is determined. Alternatively, the profiler includes a total counter for counting the combined bus cycles owned by all masters, and fewer master counters than masters, each configurable to count a selected master. Upon a profile event, the counts of the master counters, the total counter, and the realtime counter are simultaneously output to the system. Accordingly, the bandwidth consumption of the selected masters and the combined, non-selected masters, can be calculated using fewer counters.
Abstract:
A data processing system includes a bus, a plurality of devices connected to the bus, and a unit for executing data transfer between at least two of the plurality of devices via the bus, using one of a first bus cycle mode that enables data transfer with handshaking operation therebetween and a second bus cycle mode that enables stream data transfer without handshaking operation therebetween.
Abstract:
An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.
Abstract:
A method, apparatus, and system are provided for multi-link extensions and bundle skew management. According to one embodiment, multiple parallel links between two or more devices are combined into a single channel, and cells on the various links are received in a round-robin order, and variations in flight time between the various links are compensated through a timer at each receive port of the bundle.
Abstract:
A serial bus communication system for communication across the backplane of a node includes a control unit having a serial bus controller. A plurality of service units each include a serial bus terminator. A serial bus includes a discrete serial channel for each service unit. The serial channel connects the serial bus terminator to the serial bus controller. The serial bus controller is operable to direct a message for a service unit on the serial bus to only the serial channel of the service unit.
Abstract:
A method of address management in a net having a plurality of buses linked by a plurality of bus bridges where the net has only one branch bus with multiple bus bridges. A local identification address is assigned to each node on a branch bus and a bus number is assigned to each bus other than the branch bus. The bus number includes a common base and the local identification address for the node having a portal that connects to that bus.
Abstract:
A computer system has a USB bus to which one or more USB-compatible devices can connect. One or more of the USB devices has an electrical interface that includes two transmitters and, if desired, a receiver for bidirectional data transmission. The transmitters preferably are dual output, differential transmitters. The transmitters include a slower transmitter and a faster transmitter. The faster transmitter can transmit data at a rate that is faster than the slower transmitter. The electrical interface also includes an electrical termination device that is disposed between the output terminals of the two transmitters. The termination device preferably comprises a pair of multi-purpose termination resistors that can provide serial termination or parallel termination depending whether the fast or slow transmitter is used. When transmitting using the slower transmitter, the receiving USB device disables all of its transmitters and the transmitting USB device disables the output of the faster transmitter by deasserting an output enable (OE) signal to the faster transmitter. The termination device provides serial termination and the data from the slower transmitter passes through the termination device. When transmitting using the faster transmitter, both receiving and transmitting USB devices assert single ended zero (SE0) signals to their slower transmitters which forces both of the slower transmitters' output signals to a low impedance state. In this latter transmission mode, the termination device provides parallel termination, effectively functioning as a “pull-down” terminator. With parallel termination, echoes effectively are reduced or eliminated and faster data rates are thereby attainable than are generally possible with serially-terminated transmission lines.