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公开(公告)号：US5748919A
公开(公告)日：1998-05-05
申请号：US677775
申请日：1996-07-10
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
CPC分类号： G06F13/4018
摘要： A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.
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公开(公告)号：US06523080B1
公开(公告)日：2003-02-18
申请号：US09014090
申请日：1998-01-27
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
IPC分类号： G06F1342
CPC分类号： G06F13/385
摘要： A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.
摘要翻译： 提供共享总线非顺序数据排序方法和装置。 识别最大总线宽度值和最小传输值。 响应于所识别的最大总线宽度值和最小传输值来识别最小数量的子传送。 具有用于接收和/或发送数据的最大数量的码片的总线单元在多个子传送期间以预定义的顺序接收数据。 在每个数据子传送期间，相应的预定义字被传送到总线单元的每个芯片。
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3.发明授权Method and system for improving DRAM subsystem performance using burst refresh control 失效使用突发刷新控制来提高DRAM子系统性能的方法和系统公开(公告)号：US06188627B1
公开(公告)日：2001-02-13
申请号：US09374200
申请日：1999-08-13
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , William Paul Hovis , James Anthony Marcella
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , William Paul Hovis , James Anthony Marcella
IPC分类号： G11C700
CPC分类号： G11C11/406 , G11C7/1018
摘要： A method and system for improving DRAM performance using burst refresh control reduces the overhead associated with refreshing DRAM in a computer system, making the memory more available to the devices that access it. Limiting the burst cycle to less than the entire DRAM array provides a lower latency than existing full DRAM burst techniques.
摘要翻译： 使用突发刷新控制来提高DRAM性能的方法和系统减少了与计算机系统中的刷新DRAM相关联的开销，使得存储器对于访问它的设备更为可用。 将突发周期限制为小于整个DRAM阵列提供比现有的全DRAM突发技术更低的延迟。
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公开(公告)号：US06513091B1
公开(公告)日：2003-01-28
申请号：US09439586
申请日：1999-11-12
IPC分类号： G06F1314
CPC分类号： G06F13/14
摘要： A method and apparatus for routing data between bus devices, where each bus device is connected to a centralized switch via a point-to-point bus connection. The plurality of point-to-point bus connections collectively form a system bus. After a command is issued on the system bus, each bus device responds to the issued command by transmitting an address status response to a response combining logic module. The response combining logic module identifies which of the bus devices responded with a positive acknowledgment to the issued command, then forwards a device identifier of the bus device responding with the positive acknowledgment to the switch. The switch uses the device identifier returned via the response combining logic to route the data transfer associated with the issued command.
摘要翻译： 一种用于在总线设备之间路由数据的方法和设备，其中每个总线设备经由点到点总线连接连接到集中式交换机。 多个点到点总线连接共同形成系统总线。 在系统总线上发出命令之后，每个总线设备通过向响应组合逻辑模块发送地址状态响应来响应发出的命令。 响应组合逻辑模块识别哪个总线设备对所发出的命令进行肯定确认响应，然后将响应于肯定确认的总线设备的设备标识符转发给交换机。 交换机使用通过响应组合逻辑返回的设备标识符来路由与发出的命令相关联的数据传输。
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5.发明授权Redundant bit steering mechanism with delayed switchover of fetch operations during redundant device initialization 失效冗余位转向机制，在冗余设备初始化期间具有提取操作的延迟切换公开(公告)号：US06505306B1
公开(公告)日：2003-01-07
申请号：US09396973
申请日：1999-09-15
IPC分类号： H02H305
CPC分类号： G11C29/76
摘要： An apparatus, program product and method initialize a redundant memory device by delaying the switchover of non-initialization fetch operations from a failed memory device to the redundant memory device until after initialization of the redundant memory device is complete. Consequently, during initialization, the non-initialization fetch operations are directed to the failed memory device, while non-initialization store operations are directed to the redundant device.
摘要翻译： 装置，程序产品和方法通过将非初始化获取操作从故障存储器设备切换到冗余存储器设备来初始化冗余存储器件，直到冗余存储器件的初始化完成为止。 因此，在初始化期间，非初始化提取操作被定向到故障存储器设备，而非初始化存储操作被引导到冗余设备。
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6.发明授权Method and system for multilevel arbitration in a non-blocking crossbar switch 有权非阻塞交叉开关中多级仲裁的方法和系统公开(公告)号：US06628662B1
公开(公告)日：2003-09-30
申请号：US09450792
申请日：1999-11-29
IPC分类号： H04L12413
CPC分类号： H04L49/254 , H04L49/101 , H04L49/201 , H04L49/205
摘要： A method and system for arbitrating data transfers between devices connected via electronically isolated buses at a switch. In accordance with the method and system of the present invention, multiple arbitration controllers are interposed between devices and a switch to which the devices are connected, wherein each of the multiple arbitration controllers are effective to select a data transfer operation and detect collisions between said selected data transfer operations. The switch is enabled for any selected data transfer operations between which collisions are not detected. The switch is also enabled for only one of the selected data transfer operations between which collisions are detected. Any selected data transfer operations for which the switch is not enabled are deferred. The deferred data transfer operations are prioritized within the multiple arbitration controllers, such that for a subsequent selection of the deferred data transfer operations, the switch is enabled for the deferred data transfer operations.
摘要翻译： 一种用于仲裁在交换机通过电子隔离总线连接的设备之间的数据传输的方法和系统。 根据本发明的方法和系统，多个仲裁控制器被插在设备之间和设备连接的交换机之间，其中多个仲裁控制器中的每一个有效地选择数据传输操作并检测所选择的 数据传输操作。 对于未检测到碰撞的任何所选数据传输操作，该开关被使能。 只有在检测到碰撞之间的所选数据传输操作中的一个时，该开关也被使能。 任何未启用交换机的选定数据传输操作都会被延迟。 延迟数据传输操作在多个仲裁控制器内被优先排列，使得对于延迟数据传输操作的后续选择，该交换机被启用用于延迟数据传输操作。
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公开(公告)号：US06895482B1
公开(公告)日：2005-05-17
申请号：US09394011
申请日：1999-09-10
CPC分类号： G06F9/3824 , G06F3/0659 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3859
摘要： An improved computer memory subsystem determines the most efficient memory command to execute. The physical location and any address dependency of each incoming memory command to a memory controller is ascertained and that information accompanies the command for categorization into types of command. For each type of memory command, there exists a command FIFO and associated logic in which a programmable number of the memory commands are selected for comparison with each other, with the memory command currently executing, and with the memory command previously chosen for execution. The memory command having the least memory cycle performance penalty is selected for execution unless that memory command has an address dependency. If more than one memory command of that type has the least memory cycle performance penalty, then the oldest is selected for execution. Memory commands of that type are selected for execution each subsequent cycle until a valid memory command of that type is no longer available, or until a predetermined number has been executed, or until a memory command of another type has higher priority. If an address dependency exists between memory commands of different types, then memory commands of the same type of the oldest memory command is executed to avoid deadlock.
摘要翻译： 改进的计算机存储器子系统确定执行最有效的存储器命令。 确定每个传入存储器命令到存储器控制器的物理位置和任何地址依赖性，并且该信息伴随着用于分类为命令类型的命令。 对于每种类型的存储器命令，存在命令FIFO和相关联的逻辑，其中存储器命令的可编程数目被选择用于当前正在执行的存储器命令以及先前选择用于执行的存储器命令之间的比较。 选择具有最少存储周期性能损失的存储器命令用于执行，除非该存储器命令具有地址依赖性。 如果该类型的多个存储器命令具有最小的内存周期性能损失，则选择最旧的内存命令执行。 选择该类型的存储器命令用于每个后续周期执行，直到该类型的有效存储器命令不再可用，或者直到预定号码已被执行，或者直到另一类型的存储器命令具有较高优先级为止。 如果不同类型的存储器命令之间存在地址依赖关系，则执行相同类型的最旧存储器命令的存储器命令以避免死锁。
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公开(公告)号：US06963516B2
公开(公告)日：2005-11-08
申请号：US10306142
申请日：2002-11-27
申请人： Herman Lee Blackmon , John Michael Borkenhagen , Joseph Allen Kirscht , James Anthony Marcella , David Alan Shedivy
发明人： Herman Lee Blackmon , John Michael Borkenhagen , Joseph Allen Kirscht , James Anthony Marcella , David Alan Shedivy
IPC分类号： G06F12/00 , G06F13/16 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4093
CPC分类号： G06F13/1689 , G11C7/1006 , G11C7/22 , G11C11/4076 , G11C11/4093
摘要： A method and apparatus is provided which dynamically alters SDRAM memory interface timings to provide minimum read access latencies for different types of memory accesses in a memory subsystem of a computer system. The dynamic alteration of the SDRAM memory interface timings is based on workload and is determined with information from the memory controller read queue.
摘要翻译： 提供了一种方法和装置，其动态地改变SDRAM存储器接口定时以为计算机系统的存储器子系统中的不同类型的存储器访问提供最小的读访问延迟。 SDRAM存储器接口定时的动态改变基于工作负载，并且由来自存储器控制器读取队列的信息确定。
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9.发明授权Spacing periodic commands to a volatile memory for increased performance and decreased collision 失效将周期性命令间隔到易失性存储器，以提高性能和减少碰撞公开(公告)号：US08549217B2
公开(公告)日：2013-10-01
申请号：US12620065
申请日：2009-11-17
IPC分类号： G06F12/00
CPC分类号： G06F13/1689 , G11C11/40611
摘要： A periodic command spacing mechanism is provided for spacing periodic commands (e.g., refresh commands, ZQ calibration, etc.) to a volatile memory (e.g., SDRAM, DRAM, EDRAM, etc.) for increased performance and decreased collision. In one embodiment, periodic command requests are monitored and if a collision is detected between two or more of the requests, the colliding requests are spaced with respect to one another by a timer offset applied on a chip select basis. The periodic command spacing mechanism may be used in conjunction with command arbitration to make sure the periodic commands are executed without significantly impacting performance (e.g., Reads and Writes are allowed to flow). Preferably, the periodic command requests are initialized by generating an initial sequence of individual requests, each successive request in the initial sequence being generated spaced apart with respect to the previous request by a timer offset applied on a chip select basis.
摘要翻译： 提供了周期性的命令间隔机制，用于将周期性命令（例如，刷新命令，ZQ校准等）分隔到易失性存储器（例如，SDRAM，DRAM，EDRAM等）中，以提高性能和减少碰撞。 在一个实施例中，监视周期性命令请求，并且如果在两个或更多请求之间检测到冲突，则冲突请求通过以芯片选择为基础施加的定时器偏移而相对于彼此间隔开。 周期性命令间隔机制可以与命令仲裁一起使用，以确保执行周期性命令而不会显着影响性能（例如，允许读取和写入流动）。 优选地，通过产生单独请求的初始序列来初始化周期性命令请求，初始序列中的每个连续请求通过以芯片选择为基础应用的定时器偏移相对于先前请求间隔开。
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公开(公告)号：US08082396B2
公开(公告)日：2011-12-20
申请号：US11116626
申请日：2005-04-28
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F13/1642
摘要： A method, apparatus, system, and signal-bearing medium that, in an embodiment, select a command to send to memory. In an embodiment, the oldest command in a write queue that does not collide with a conflict queue is sent to memory and added to the conflict queue if some or all of the following are true: all of the commands in the read queue collide with the conflict queue, any read command incoming from the processor does not collide with the write queue, the number of commands in the write queue is greater than a first threshold, and all commands in the conflict queue have been present for less than a second threshold. In an embodiment, a command does not collide with a queue if the command does not access the same cache line in memory as the commands in the queue. In this way, in an embodiment, write commands are sent to the memory at a time that reduces the impact on the performance of read commands.
摘要翻译： 在一个实施例中，选择要发送到存储器的命令的方法，装置，系统和信号承载介质。 在一个实施例中，写入队列中与冲突队列不冲突的最早的命令被发送到存储器，并且如果以下部分或全部为真，则将其添加到冲突队列中：读队列中的所有命令与 冲突队列，从处理器传入的任何读取命令都不会与写入队列冲突，写入队列中的命令数量大于第一个阈值，并且冲突队列中的所有命令都存在少于第二个阈值。 在一个实施例中，如果命令不访问存储器中与队列中的命令相同的高速缓存行，则命令不与队列冲突。 以这种方式，在一个实施例中，写入命令在减少对读取命令的性能的影响的时刻被发送到存储器。
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