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公开(公告)号：US20080301687A1
公开(公告)日：2008-12-04
申请号：US12172910
申请日：2008-07-14
申请人： Anuj B. Gosalia , Steve Pronovost
发明人： Anuj B. Gosalia , Steve Pronovost
IPC分类号： G06F9/46
CPC分类号： G06F9/5038 , G06F9/30087 , G06F9/461 , G06F9/4843 , G06F9/5016 , G06F9/544 , G06F9/546 , Y02D10/22 , Y02D10/24
摘要： Techniques for minimizing coprocessor “starvation,” and for effectively scheduling processing in a coprocessor for greater efficiency and power. A run list is provided allowing a coprocessor to switch from one task to the next, without waiting for CPU intervention. A method called “surface faulting” allows a coprocessor to fault at the beginning of a large task rather than somewhere in the middle of the task. DMA control instructions, namely a “fence,” a “trap” and a “enable/disable context switching,” can be inserted into a processing stream to cause a coprocessor to perform tasks that enhance coprocessor efficiency and power. These instructions can also be used to build high-level synchronization objects. Finally, a “flip” technique is described that can switch a base reference for a display from one location to another, thereby changing the entire display surface.
摘要翻译： 用于最小化协处理器“饥饿”的技术，并且用于在协处理器中有效地调度处理以获得更高的效率和功率。 提供运行列表，允许协处理器从一个任务切换到下一个任务，而不必等待CPU干预。 称为“表面故障”的方法允许协处理器在大任务开始时发生故障，而不是在任务中间的任何地方。 可以将DMA控制指令，即“围栏”，“陷阱”和“启用/禁用上下文切换”插入到处理流中，以使协处理器执行增强协处理器效率和功率的任务。 这些指令也可用于构建高级同步对象。 最后，描述了一种“翻转”技术，其可以将显示器的基准基准从一个位置切换到另一个位置，从而改变整个显示表面。
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公开(公告)号：US07421694B2
公开(公告)日：2008-09-02
申请号：US10763778
申请日：2004-01-22
申请人： Anuj B. Gosalia , Steve Pronovost
发明人： Anuj B. Gosalia , Steve Pronovost
CPC分类号： G06F9/4843 , G06F9/4881 , G06F9/5016 , Y02D10/22 , Y02D10/24
摘要： Techniques for minimizing coprocessor “starvation,” and for effectively scheduling processing in a coprocessor for greater efficiency and power. A run list is provided allowing a coprocessor to switch from one task to the next, without waiting for CPU intervention. A method called “surface faulting” allows a coprocessor to fault at the beginning of a large task rather than somewhere in the middle of the task. DMA control instructions, namely a “fence,” a “trap” and a “enable/disable context switching,” can be inserted into a processing stream to cause a coprocessor to perform tasks that enhance coprocessor efficiency and power. These instructions can also be used to build high-level synchronization objects. Finally, a “flip” technique is described that can switch a base reference for a display from one location to another, thereby changing the entire display surface.
摘要翻译： 用于最小化协处理器“饥饿”的技术，并且用于在协处理器中有效地调度处理以获得更高的效率和功率。 提供运行列表，允许协处理器从一个任务切换到下一个任务，而不必等待CPU干预。 称为“表面故障”的方法允许协处理器在大任务开始时发生故障，而不是在任务中间的任何地方。 可以将DMA控制指令，即“围栏”，“陷阱”和“启用/禁用上下文切换”插入到处理流中，以使协处理器执行增强协处理器效率和功率的任务。 这些指令也可用于构建高级同步对象。 最后，描述了一种“翻转”技术，其可以将显示器的基准基准从一个位置切换到另一个位置，从而改变整个显示表面。
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公开(公告)号：US07830387B2
公开(公告)日：2010-11-09
申请号：US11557301
申请日：2006-11-07
CPC分类号： G06F9/4843 , G06F3/14 , G06F9/461 , G06F9/5016 , G06F9/5061 , G06F9/544 , G06T7/0004 , G09G5/363
摘要： Systems and methods that independently control divided and/or isolated processing resources of a Graphical Processing Unit (GPU). Synchronization primitives for processing are shared among such resources to process interaction with the engines and their associated different requirements (e.g. different language). Accordingly, independent threads can be created against particular nodes (e.g., a video engine node, 3D engine node), wherein multiple engines can exist under a single node, and independent control can subsequently be exerted upon the plurality of engines associated with the GPU.
摘要翻译： 独立控制图形处理单元（GPU）的分割和/或隔离处理资源的系统和方法。 用于处理的同步原语在这些资源之间共享以处理与引擎及其相关联的不同要求（例如不同语言）的交互。 因此，可以针对特定节点（例如，视频引擎节点，3D引擎节点）创建独立线程，其中多个引擎可以存在于单个节点下，并且随后可以在与GPU相关联的多个引擎上施加独立控制。
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公开(公告)号：US20100122259A1
公开(公告)日：2010-05-13
申请号：US12657278
申请日：2010-01-15
申请人： Anuj B. Gosalia , Steve Pronovost
发明人： Anuj B. Gosalia , Steve Pronovost
IPC分类号： G06F9/46 , G06F15/167
CPC分类号： G06F9/5038 , G06F9/30087 , G06F9/461 , G06F9/4843 , G06F9/5016 , G06F9/544 , G06F9/546 , Y02D10/22 , Y02D10/24
摘要： Systems and methods are provided for scheduling the processing of a coprocessor whereby applications can submit tasks to a scheduler, and the scheduler can determine how much processing each application is entitled to as well as an order for processing. In connection with this process, tasks that require processing can be stored in physical memory or in virtual memory that is managed by a memory manager. The invention also provides various techniques of determining whether a particular task is ready for processing. A “run list” may be employed to ensure that the coprocessor does not waste time between tasks or after an interruption. The invention also provides techniques for ensuring the security of a computer system, by not allowing applications to modify portions of memory that are integral to maintaining the proper functioning of system operations.
摘要翻译： 提供了用于调度协处理器的处理的系统和方法，由此应用可以将任务提交给调度器，并且调度器可以确定每个应用程序被处理多少处理以及处理顺序。 关于这个过程，需要处理的任务可以被存储在由存储器管理器管理的物理存储器或虚拟存储器中。 本发明还提供了确定特定任务是否准备好进行处理的各种技术。 可以使用“运行列表”来确保协处理器不会在任务之间或在中断之后浪费时间。 本发明还提供了用于确保计算机系统的安全性的技术，不允许应用修改为维持系统操作的正常功能而整体的部分存储器。
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5.发明授权Systems and methods for scheduling coprocessor resources in a computing system 有权在计算系统中调度协处理器资源的系统和方法公开(公告)号：US07444637B2
公开(公告)日：2008-10-28
申请号：US10777797
申请日：2004-02-12
CPC分类号： G06F13/30 , G06F9/4881 , G06F9/5016
摘要： Systems and methods for scheduling coprocessing resources in a computing system are provided without redesigning the coprocessor. In various embodiments, a system of preemptive multitasking is provided achieving benefits over cooperative multitasking by any one or more of (1) executing rendering commands sent to the coprocessor in a different order than they were submitted by applications; (2) preempting the coprocessor during scheduling of non-interruptible hardware; (3) allowing user mode drivers to build work items using command buffers in a way that does not compromise security; (4) preparing DMA buffers for execution while the coprocessor is busy executing a previously prepared DMA buffer; (5) resuming interrupted DMA buffers; and (6) reducing the amount of memory needed to run translated DMA buffers.
摘要翻译： 提供了一种用于在计算系统中调度协处理资源的系统和方法，而不重新设计协处理器。 在各种实施例中，提供了一种抢占式多任务的系统，其通过以下方式中的任何一个或多个实现协作多任务的优点：（1）以与应用提交的顺序不同的顺序执行发送到协处理器的呈现命令; （2）在调度不可中断硬件期间抢占协处理器; （3）允许用户模式驱动程序以不损害安全性的方式使用命令缓冲区构建工作项; （4）在协处理器忙于执行预先准备的DMA缓冲器时，准备执行DMA缓冲器; （5）恢复中断DMA缓冲区; 和（6）减少运行转换的DMA缓冲区所需的内存量。
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6.发明授权Building a run list for a coprocessor based on rules when the coprocessor switches from one context to another context 有权当协处理器从一个上下文切换到另一个上下文时，基于规则构建协处理器的运行列表公开(公告)号：US09298498B2
公开(公告)日：2016-03-29
申请号：US12172910
申请日：2008-07-14
申请人： Anuj B. Gosalia , Steve Pronovost
发明人： Anuj B. Gosalia , Steve Pronovost
CPC分类号： G06F9/5038 , G06F9/30087 , G06F9/461 , G06F9/4843 , G06F9/5016 , G06F9/544 , G06F9/546 , Y02D10/22 , Y02D10/24
摘要： Techniques for minimizing coprocessor “starvation,” and for effectively scheduling processing in a coprocessor for greater efficiency and power. A run list is provided allowing a coprocessor to switch from one task to the next, without waiting for CPU intervention. A method called “surface faulting” allows a coprocessor to fault at the beginning of a large task rather than somewhere in the middle of the task. DMA control instructions, namely a “fence,” a “trap” and a “enable/disable context switching,” can be inserted into a processing stream to cause a coprocessor to perform tasks that enhance coprocessor efficiency and power. These instructions can also be used to build high-level synchronization objects. Finally, a “flip” technique is described that can switch a base reference for a display from one location to another, thereby changing the entire display surface.
摘要翻译： 用于最小化协处理器“饥饿”的技术，并且用于在协处理器中有效地调度处理以获得更高的效率和功率。 提供运行列表，允许协处理器从一个任务切换到下一个任务，而不必等待CPU干预。 称为“表面故障”的方法允许协处理器在大任务开始时发生故障，而不是在任务中间的任何地方。 可以将DMA控制指令，即“围栏”，“陷阱”和“启用/禁用上下文切换”插入到处理流中，以使协处理器执行增强协处理器效率和功率的任务。 这些指令也可用于构建高级同步对象。 最后，描述了一种“翻转”技术，其可以将显示器的基准基准从一个位置切换到另一个位置，从而改变整个显示表面。
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公开(公告)号：US08671411B2
公开(公告)日：2014-03-11
申请号：US12657278
申请日：2010-01-15
申请人： Anuj B. Gosalia , Steve Pronovost
发明人： Anuj B. Gosalia , Steve Pronovost
CPC分类号： G06F9/5038 , G06F9/30087 , G06F9/461 , G06F9/4843 , G06F9/5016 , G06F9/544 , G06F9/546 , Y02D10/22 , Y02D10/24
摘要： Systems and methods are provided for scheduling the processing of a coprocessor whereby applications can submit tasks to a scheduler, and the scheduler can determine how much processing each application is entitled to as well as an order for processing. In connection with this process, tasks that require processing can be stored in physical memory or in virtual memory that is managed by a memory manager. The invention also provides various techniques of determining whether a particular task is ready for processing. A “run list” may be employed to ensure that the coprocessor does not waste time between tasks or after an interruption. The invention also provides techniques for ensuring the security of a computer system, by not allowing applications to modify portions of memory that are integral to maintaining the proper functioning of system operations.
摘要翻译： 提供了用于调度协处理器的处理的系统和方法，由此应用可以将任务提交给调度器，并且调度器可以确定每个应用程序被处理多少处理以及处理顺序。 关于这个过程，需要处理的任务可以被存储在由存储器管理器管理的物理存储器或虚拟存储器中。 本发明还提供了确定特定任务是否准备好进行处理的各种技术。 可以使用“运行列表”来确保协处理器不会在任务之间或在中断之后浪费时间。 本发明还提供了用于确保计算机系统的安全性的技术，不允许应用修改为维持系统操作的正常功能而整体的部分存储器。
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公开(公告)号：US07673304B2
公开(公告)日：2010-03-02
申请号：US10763777
申请日：2004-01-22
申请人： Anuj B. Gosalia , Steve Pronovost
发明人： Anuj B. Gosalia , Steve Pronovost
IPC分类号： G06F9/46 , G06F15/167
CPC分类号： G06F9/5038 , G06F9/30087 , G06F9/461 , G06F9/4843 , G06F9/5016 , G06F9/544 , G06F9/546 , Y02D10/22 , Y02D10/24
摘要： Systems and methods are provided for scheduling the processing of a coprocessor whereby applications can submit tasks to a scheduler, and the scheduler can determine how much processing each application is entitled to as well as an order for processing. In connection with this process, tasks that require processing can be stored in physical memory or in virtual memory that is managed by a memory manager. The invention also provides various techniques of determining whether a particular task is ready for processing. A “run list” may be employed to ensure that the coprocessor does not waste time between tasks or after an interruption. The invention also provides techniques for ensuring the security of a computer system, by not allowing applications to modify portions of memory that are integral to maintaining the proper functioning of system operations.
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公开(公告)号：US20080109810A1
公开(公告)日：2008-05-08
申请号：US11557301
申请日：2006-11-07
IPC分类号： G06F9/50
CPC分类号： G06F9/4843 , G06F3/14 , G06F9/461 , G06F9/5016 , G06F9/5061 , G06F9/544 , G06T7/0004 , G09G5/363
摘要： Systems and methods that independently control divided and/or isolated processing resources of a Graphical Processing Unit (GPU). Synchronization primitives for processing are shared among such resources to process interaction with the engines and their associated different requirements (e.g. different language). Accordingly, independent threads can be created against particular nodes (e.g., a video engine node, 3D engine node), wherein multiple engines can exist under a single node, and independent control can subsequently be exerted upon the plurality of engines associated with the GPU.
摘要翻译： 独立控制图形处理单元（GPU）的分割和/或隔离处理资源的系统和方法。 用于处理的同步原语在这些资源之间共享以处理与引擎及其相关联的不同要求（例如不同语言）的交互。 因此，可以针对特定节点（例如，视频引擎节点，3D引擎节点）创建独立线程，其中多个引擎可以存在于单个节点下，并且随后可以在与GPU相关联的多个引擎上施加独立控制。
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公开(公告)号：US09342322B2
公开(公告)日：2016-05-17
申请号：US13230436
申请日：2011-09-12
申请人： Blake D. Pelton , Amar Patel , Steve Pronovost
发明人： Blake D. Pelton , Amar Patel , Steve Pronovost
CPC分类号： G06T11/40 , G06F9/44 , G06F9/451 , G06F17/00 , G06T1/00 , G06T1/20 , G06T15/00 , G06T15/005 , G09G5/36 , G09G5/363 , G09G2360/122
摘要： A method for tile-based rendering of content. Content may be rendered in a memory region organized as multiple tiles. In scenarios in which content is generated in layers, for operations that involve compositing image layers, an order in which portions of the image are processed may be selected to reduce the aggregate number of memory accesses times, which in turn may improve the performance of a computer that uses tile-based rendering. An image may be processed such that operations relating to rendering portions of different layers corresponding to the same tile are performed sequentially. Such processing may be used in a computer with a graphics processing unit that supports tile-based rendering, and may be particularly well suited for computers with a slate form factor. An interface to a graphics processing utility within the computer may provide a flag to allow an application to specify whether operations may be reordered.
摘要翻译： 一种基于图块的内容呈现方法。 内容可以在被组织为多个瓦片的存储器区域中呈现。 在层内生成内容的情况下，对于涉及合成图像层的操作，可以选择处理图像的哪些部分的顺序来减少存储器访问次数的总数，这又可以提高图像的性能 计算机使用基于瓦片的渲染。 可以处理图像，使得与依次对应的不同层的渲染部分相关的操作被顺序地执行。 这种处理可以在具有支持基于瓦片的呈现的图形处理单元的计算机中使用，并且可以特别适合于具有平板形状因数的计算机。 与计算机内的图形处理实用程序的接口可以提供标志以允许应用程序指定是否可以重新排序操作。
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