公开(公告)号：US11100028B1

公开(公告)日：2021-08-24

申请号：US16858871

申请日：2020-04-27

申请人： Apex Semiconductor

发明人： Suresh Subramaniam ,  Alfred Yeung

IPC分类号： G06F13/40 ,  G06F13/42

摘要： A flexible standards-based bridge or switch chiplet facilitates heterogeneous integration of chiplets that support different physical layer (PHY) interfaces and communication protocols. The bridge chiplet is configured with multiple PHY interfaces and associated adapter logic and translation logic for translation between different PHY interfaces and protocols. The bridge chiplet can be programmed to serve as a die-to-die interconnect bridge that routes data between multiple chiplets supporting different PHYs and interconnect protocols. Some embodiments of the bridge chiplet can serve solely as a PHY bridge, while others may serve as a bridge for both PHYs and protocols.

公开(公告)号：US11295057B1

公开(公告)日：2022-04-05

申请号：US17172200

申请日：2021-02-10

申请人： Apex Semiconductor

发明人： Minkyu Kim ,  Alfred Yeung ,  Pingchun Chiang ,  Suresh Subramaniam ,  Pravin Chingudi

IPC分类号： G06F30/398 ,  G06F111/20 ,  G06F119/02

摘要： A corner prediction system applies data generated through discrete process, voltage, and temperature (PVT) corner prediction to achieve highly accurate continuous corner prediction coverage. Embodiments of the corner prediction system can be trained to generate accurate performance metric prediction for a continuous range of PVT corners within a design space given a set of available pre-trained PVT corners. The corner prediction system can address the need to provide accurate continuous timing prediction coverage of design operating conditions (represented by PVT corners) through the availability of discrete PVT corners.

公开(公告)号：US11036908B1

公开(公告)日：2021-06-15

申请号：US16894992

申请日：2020-06-08

申请人： Apex Semiconductor

发明人： Pravin Chingudi ,  Suresh Subramaniam ,  Alfred Yeung ,  Minkyu Kim ,  Pingchun Chiang

IPC分类号： G06F30/00 ,  G06F30/3312 ,  G06N20/00 ,  G06F30/3315 ,  G06N5/04 ,  G06F119/12

摘要： Techniques improve integrated circuit design by employing multi-operating condition frequency prediction for statically timed designs through spice-based timing path labeling and statistical analysis. Design management component (DMC) can randomly determine and generate sample timing paths based on parameters of characteristics associated with the sample timing paths, the parameters determined based on random seed values; simulate responses of the sample timing paths; and generate vectorized data based on the simulated responses. DMC determines a trained model representing timing path properties and operating conditions of sample timing paths based on statistical analysis of vectorized data. Static timing analysis (STA) component can perform STA on design information of integrated circuitry design and determine an operating condition of a timing path of the design based on the STA. DMC can determine or predict another operating condition(s) associated with the design based on the operating condition and the trained model.

公开(公告)号：US11475194B1

公开(公告)日：2022-10-18

申请号：US16778537

申请日：2020-01-31

申请人： Apex Semiconductor

发明人： Alfred Yeung ,  Minkyu Kim ,  Suresh Subramaniam ,  Pravin Chingudi

IPC分类号： G06F30/3315 ,  G06F30/3308 ,  G06F119/12

摘要： Techniques improve integrated circuit design by employing multi-operating condition frequency prediction for statically timed designs through statistical analysis. A design management component (DMC) can determine a trained model representing timing path properties and operating conditions of agnostic timing paths based on an analysis of vectorized data that represents timing path information associated with the agnostic timing paths. DMC can perform statistical regression on the vectorized data to facilitate training the trained model. A static timing analysis (STA) component can perform STA on design information associated with the integrated circuitry design and determine an operating condition of a timing path of the integrated circuitry design based on the STA. DMC can predict or determine at least one other operating condition associated with the integrated circuitry design based on the operating condition and the trained model.

公开(公告)号：US11386252B1

公开(公告)日：2022-07-12

申请号：US17194358

申请日：2021-03-08

申请人： Apex Semiconductor

发明人： Pravin Chingudi ,  Suresh Subramaniam ,  Alfred Yeung ,  Minkyu Kim ,  Pingchun Chiang

IPC分类号： G06F30/00 ,  G06F30/3312 ,  G06F30/3315 ,  G06N5/04 ,  G06N20/00 ,  G06F119/12

摘要： Techniques improve integrated circuit design by employing multi-operating condition frequency prediction for statically timed designs through spice-based timing path labeling and statistical analysis. Design management component (DMC) can randomly determine and generate sample timing paths based on parameters of characteristics associated with the sample timing paths, the parameters determined based on random seed values; simulate responses of the sample timing paths; and generate vectorized data based on the simulated responses. DMC determines a trained model representing timing path properties and operating conditions of sample timing paths based on statistical analysis of vectorized data. Static timing analysis (STA) component can perform STA on design information of integrated circuitry design and determine an operating condition of a timing path of the design based on the STA. DMC can determine or predict another operating condition(s) associated with the design based on the operating condition and the trained model.