公开(公告)号：US11080188B1

公开(公告)日：2021-08-03

申请号：US15939099

申请日：2018-03-28

Applicant: Apple Inc.

Inventor： Jonathan Y. Tong ,  Ronald P. Hall ,  Christopher Colletti ,  David E. Kroesche ,  James N. Hardage, Jr.

IPC: G06F12/0815 ,  G06F12/1036 ,  G06F12/0808 ,  G06F12/1009

Abstract: A system and method for efficiently handling maintenance requests among multiple processors. In various embodiments, a given processor of multiple processors receives a maintenance request. If maintenance requests are not currently being blocked, then the given processor determines a type of the maintenance request and updates one or more maintenance type counters based on the type. If one or more counters exceed a threshold, an indication is generated specifying maintenance requests received at a later time are to be held. The received maintenance request is processed. Different types of maintenance requests are used for invalidating entries in the instruction cache, for invalidating entries in a TLB and for synchronizing page table updates. Afterward, software applications continue processing. Forward progress of the software applications is measured using one or more metrics. If forward progress has been achieved, then one or more maintenance type counters are reset.

公开(公告)号：US11886340B1

公开(公告)日：2024-01-30

申请号：US17818660

申请日：2022-08-09

Applicant: Apple Inc.

Inventor： Jonathan Y. Tong ,  David E. Kroesche ,  Brett S. Feero

IPC: G06F12/08 ,  G06F12/0802 ,  G06F3/06

CPC classification number: G06F12/0802 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0679 ,  G06F2212/60

Abstract: A processor configured for real-time transaction processing is disclosed. A processor circuit includes configuration registers that designate a first range of physical memory addresses as reserved for real-time memory requests and a second, non-overlapping range of physical memory addresses that are shared between real-time and non-real-time memory requests. In response to determining that a memory request is associated with an address in the first range, the processor tags the request as a real-time request. The configuration registers may also store information designating portions of one or more cache memories and one or more buffers as being reserved for real-time memory requests. During arbitration, real-time memory requests are given priority over older, non-real-time memory requests.

公开(公告)号：US20250094355A1

公开(公告)日：2025-03-20

申请号：US18544110

申请日：2023-12-18

Applicant: Apple Inc.

Inventor： Brett S. Feero ,  Brian T. Mokrzycki ,  Jonathan Y. Tong ,  Michael D. Snyder ,  James N. Hardage

IPC: G06F12/1027

Abstract: Techniques are disclosed relating to using an instruction (e.g., a pre-translate instruction) to lock translations in TLB entries. The execution of the instruction may include storing translation information in a TLB entry, and setting an indication that the entry is locked. The processor circuitry may receive an invalidate command corresponding to the locked entry. Processor circuitry may, in response to the invalidate command and based on the indication that the entry is locked, maintain the locked entry in a valid state in the translation lookaside buffer circuitry, notwithstanding the invalidate command. Processor circuitry may be further configured to modify previously-stored data in a given entry to aggregate, in the entry, translation information for multiple regions of the second address space.

公开(公告)号：US10552323B1

公开(公告)日：2020-02-04

申请号：US16126812

申请日：2018-09-10

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Todd A. Venton ,  Jonathan Y. Tong ,  David E. Kroesche

IPC: G06F12/08 ,  G06F12/0804 ,  G06F12/0891 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0866

Abstract: Various embodiments of a method and apparatus for flushing a cache are disclosed. In a system, a cache memory is accessible by an execution circuit. The execution circuit executes instructions and may utilize data and/or instructions stored in the cache. A flush circuit is also coupled to the cache. Responsive to execution of a power down instruction by the execution circuit, the flush circuit performs a cache flush. If a control state is asserted in a control register, the flush circuit generates a dummy event upon completing the cache flush. Responsive to generating the dummy event, a processor core that includes the execution circuit is inhibited from being powered down.