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1.发明授权Distributed gain stage for high speed high resolution pipeline analog to digital converters 有权分布式增益级用于高速高分辨率管道模数转换器公开(公告)号：US09191019B2
公开(公告)日：2015-11-17
申请号：US14658333
申请日：2015-03-16
Applicant: Apple Inc.
Inventor： Mansour Keramat , Friedel Gerfers
CPC classification number: H03M1/08 , H03M1/002 , H03M1/0617 , H03M1/121 , H03M1/1245 , H03M1/167 , H03M1/36 , H03M1/70
Abstract: In an embodiment, multiple MDAC stages are coupled in parallel to form an MDAC having the desired gain and capacitor size. Each stage may include capacitors and an OTA that are much smaller than the corresponding capacitors and OTA would be for a large single stage. Interconnect for each stage may be shorter than the single stage case, and thus the parasitic resistance and capacitance may be lower. Power consumption may be reduced, and performance of the amplifier may be increased, due to the reduced parasitic resistance and capacitance. The area occupied by the circuitry may be lower as well. Process variation within a given stage may be lower. The process variation between stages may induce noise in the output, but the parallel connection of the stages may serve to reduce the noise, in some embodiments.
Abstract translation: 在一个实施例中，多个MDAC级并联耦合以形成具有所需增益和电容器大小的MDAC。 每个阶段可以包括电容器和比对应的电容器小得多的OTA，并且OTA将用于大的单级。 每个级的互连可能比单级情况短，因此寄生电阻和电容可能较低。 由于降低的寄生电阻和电容，功耗可能会降低，放大器的性能可能会增加。 电路占用的面积也可能较低。 给定阶段内的工艺变化可能较低。 在一些实施例中，级之间的过程变化可能导致输出中的噪声，但是级的并联可以用于减少噪声。
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2.发明申请Distributed Gain Stage for High Speed High Resolution Pipeline Analog to Digital Converters 有权用于高速高分辨率管道模数转换器的分布式增益级公开(公告)号：US20150263745A1
公开(公告)日：2015-09-17
申请号：US14658333
申请日：2015-03-16
Applicant: Apple Inc.
Inventor： Mansour Keramat , Friedel Gerfers
CPC classification number: H03M1/08 , H03M1/002 , H03M1/0617 , H03M1/121 , H03M1/1245 , H03M1/167 , H03M1/36 , H03M1/70
Abstract: In an embodiment, multiple MDAC stages are coupled in parallel to form an MDAC having the desired gain and capacitor size. Each stage may include capacitors and an OTA that are much smaller than the corresponding capacitors and OTA would be for a large single stage. Interconnect for each stage may be shorter than the single stage case, and thus the parasitic resistance and capacitance may be lower. Power consumption may be reduced, and performance of the amplifier may be increased, due to the reduced parasitic resistance and capacitance. The area occupied by the circuitry may be lower as well. Process variation within a given stage may be lower. The process variation between stages may induce noise in the output, but the parallel connection of the stages may serve to reduce the noise, in some embodiments.
Abstract translation: 在一个实施例中，多个MDAC级并联耦合以形成具有所需增益和电容器大小的MDAC。 每个阶段可以包括电容器和比对应的电容器小得多的OTA，并且OTA将用于大的单级。 每个级的互连可能比单级情况短，因此寄生电阻和电容可能较低。 由于降低的寄生电阻和电容，功耗可能会降低，放大器的性能可能会增加。 电路占用的面积也可能较低。 给定阶段内的工艺变化可能较低。 在一些实施例中，级之间的过程变化可能导致输出中的噪声，但是级的并联可以用于减少噪声。
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