公开(公告)号：US20140169075A1

公开(公告)日：2014-06-19

申请号：US13717870

申请日：2012-12-18

Applicant: APPLE INC.

Inventor： Ajay Bhatia ,  Hang Huang

IPC: G11C5/14 ,  G11C11/00 ,  G11C7/00

CPC classification number: G11C5/147 ,  G11C7/00 ,  G11C11/00 ,  G11C11/417

Abstract: A voltage source controller for a memory array includes an input coupled to a voltage source, an output coupled to one or more memory cells of a memory array, where the output is configured to provide a cell source voltage to the memory cells. The controller also includes a switch circuit configured to: receive a retention enable signal, a write assist enable signal, and a standard mode enable signal; and based on the retention enable signal, write assist enable signal, and standard mode enable signal, selectively set the cell source voltage for one or more of the memory cells to one of: a retention voltage, a write assist voltage, or a standard mode voltage, where the retention voltage and the write assist voltage are less than the standard mode voltage.

Abstract translation: 用于存储器阵列的电压源控制器包括耦合到电压源的输入端，耦合到存储器阵列的一个或多个存储器单元的输出，其中输出被配置为向存储器单元提供单元源电压。 控制器还包括一个开关电路，其被配置为：接收保持使能信号，写辅助使能信号和标准模式使能信号; 并且基于保持使能信号，写入辅助使能信号和标准模式使能信号，选择性地将一个或多个存储器单元的单元电源电压设置为以下之一：保持电压，写入辅助电压或标准模式 电压，其中保持电压和写入辅助电压小于标准模式电压。

公开(公告)号：US08964490B2

公开(公告)日：2015-02-24

申请号：US13761646

申请日：2013-02-07

Applicant: Apple Inc.

Inventor： Daniel C Chow ,  Hang Huang ,  Ajay Kumar Bhatia ,  Steven C Sullivan

IPC: G11C7/12 ,  G11C7/10 ,  G11C5/14 ,  G11C11/419

CPC classification number: G11C7/1096 ,  G11C5/145 ,  G11C11/419

Abstract: Embodiments of a memory are disclosed that may allow for a negative boost of data lines during a write. The memory device may include a data input circuit, an address decode circuit and a plurality of sub-arrays. Each of the sub-arrays may include a plurality of columns, a write selection circuit, a first write driver circuit, a second write driver circuit, and a boost circuit. Each of the columns may include a plurality of data storage cells. The write selection circuit may select a column of the plurality of columns. Each of the write driver circuits may be configured to discharge a data line of a selected column into a common node. The boost circuit may be configured to initialize the common node to the first voltage level and couple the common node to a second voltage level, where the second voltage level is lower than the first voltage level.

Abstract translation: 公开了可以在写入期间允许数据线的负升压的存储器的实施例。 存储器件可以包括数据输入电路，地址解码电路和多个子阵列。 每个子阵列可以包括多个列，写入选择电路，第一写入驱动器电路，第二写入驱动器电路和升压电路。 每个列可以包括多个数据存储单元。 写选择电路可以选择多列的列。 写入驱动器电路中的每一个可以被配置为将所选列的数据线放电到公共节点中。 升压电路可以被配置为将公共节点初始化为第一电压电平并将公共节点耦合到第二电压电平，其中第二电压电平低于第一电压电平。

公开(公告)号：US08885393B2

公开(公告)日：2014-11-11

申请号：US13717870

申请日：2012-12-18

Applicant: Apple Inc.

Inventor： Ajay Bhatia ,  Hang Huang

IPC: G11C11/00 ,  G11C7/00 ,  G11C5/14

CPC classification number: G11C5/147 ,  G11C7/00 ,  G11C11/00 ,  G11C11/417

Abstract: A voltage source controller for a memory array includes an input coupled to a voltage source, an output coupled to one or more memory cells of a memory array, where the output is configured to provide a cell source voltage to the memory cells. The controller also includes a switch circuit configured to: receive a retention enable signal, a write assist enable signal, and a standard mode enable signal; and based on the retention enable signal, write assist enable signal, and standard mode enable signal, selectively set the cell source voltage for one or more of the memory cells to one of: a retention voltage, a write assist voltage, or a standard mode voltage, where the retention voltage and the write assist voltage are less than the standard mode voltage.

Abstract translation: 用于存储器阵列的电压源控制器包括耦合到电压源的输入端，耦合到存储器阵列的一个或多个存储器单元的输出，其中输出被配置为向存储器单元提供单元源电压。 控制器还包括一个开关电路，其被配置为：接收保持使能信号，写辅助使能信号和标准模式使能信号; 并且基于保持使能信号，写入辅助使能信号和标准模式使能信号，选择性地将一个或多个存储器单元的单元电源电压设置为以下之一：保持电压，写入辅助电压或标准模式 电压，其中保持电压和写入辅助电压小于标准模式电压。

公开(公告)号：US20140219009A1

公开(公告)日：2014-08-07

申请号：US13761646

申请日：2013-02-07

Applicant: APPLE INC.

Inventor： Daniel C Chow ,  Hang Huang ,  Ajay Kumar Bhatia ,  Steven C Sullivan

IPC: G11C7/10 ,  G11C11/412

CPC classification number: G11C7/1096 ,  G11C5/145 ,  G11C11/419

Abstract: Embodiments of a memory are disclosed that may allow for a negative boost of data lines during a write. The memory device may include a data input circuit, an address decode circuit and a plurality of sub-arrays. Each of the sub-arrays may include a plurality of columns, a write selection circuit, a first write driver circuit, a second write driver circuit, and a boost circuit. Each of the columns may include a plurality of data storage cells. The write selection circuit may select a column of the plurality of columns. Each of the write driver circuits may configured to discharge a data line of a selected column into a common node. The boost circuit may be configured to initialize the common node to the first voltage level and couple the common node to a second voltage level, where the second voltage level is lower than the first voltage level.

Abstract translation: 公开了可以在写入期间允许数据线的负升压的存储器的实施例。 存储器件可以包括数据输入电路，地址解码电路和多个子阵列。 每个子阵列可以包括多个列，写入选择电路，第一写入驱动器电路，第二写入驱动器电路和升压电路。 每个列可以包括多个数据存储单元。 写选择电路可以选择多列的列。 每个写入驱动器电路可以被配置为将所选列的数据线放电到公共节点中。 升压电路可以被配置为将公共节点初始化为第一电压电平并将公共节点耦合到第二电压电平，其中第二电压电平低于第一电压电平。