公开(公告)号：US20240256280A1

公开(公告)日：2024-08-01

申请号：US18586186

申请日：2024-02-23

Applicant: Apple Inc.

Inventor： Pruthivi Vuyyuru ,  Ian D. Kountanis

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30134

Abstract: An apparatus includes a processor circuit that includes a return address stack circuit, a return prediction circuit, and a fetch control circuit. The return prediction circuit is configured to store, for previously accessed return addresses, fetch parameters for next fetch addresses. The fetch control circuit is configured to in response to a fetch of a call instruction, push a return address onto the return address stack circuit. In response to a fetch of a return instruction that corresponds to the call instruction, the fetch control circuit is further configured to retrieve the return address from the return address stack circuit, and to create, using the return address and fetch parameters retrieved from the return prediction circuit, a next fetch request to retrieve instructions subsequent to the return instruction.

公开(公告)号：US11941401B1

公开(公告)日：2024-03-26

申请号：US17806234

申请日：2022-06-09

Applicant: Apple Inc.

Inventor： Pruthivi Vuyyuru ,  Ian D. Kountanis

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30134

Abstract: An apparatus includes a processor circuit that includes a return address stack circuit, a return prediction circuit, and a fetch control circuit. The return prediction circuit is configured to store, for previously accessed return addresses, fetch parameters for next fetch addresses. The fetch control circuit is configured to in response to a fetch of a call instruction, push a return address onto the return address stack circuit. In response to a fetch of a return instruction that corresponds to the call instruction, the fetch control circuit is further configured to retrieve the return address from the return address stack circuit, and to create, using the return address and fetch parameters retrieved from the return prediction circuit, a next fetch request to retrieve instructions subsequent to the return instruction.

公开(公告)号：US09626185B2

公开(公告)日：2017-04-18

申请号：US13774093

申请日：2013-02-22

Applicant: Apple Inc.

Inventor： Shyam Sundar ,  Ian D. Kountanis ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Wei-Han Lien ,  Ramesh B. Gunna

IPC: G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC classification number: G06F9/30054 ,  G06F9/30181 ,  G06F9/382 ,  G06F9/3842 ,  G06F9/3844

Abstract: Various techniques for processing and pre-decoding branches within an IT instruction block. Instructions are fetched and cached in an instruction cache, and pre-decode bits are generated to indicate the presence of an IT instruction and the likely boundaries of the IT instruction block. If an unconditional branch is detected within the likely boundaries of an IT instruction block, the unconditional branch is treated as if it were a conditional branch. The unconditional branch is sent to the branch direction predictor and the predictor generates a branch direction prediction for the unconditional branch.

公开(公告)号：US20230023860A1

公开(公告)日：2023-01-26

申请号：US17382123

申请日：2021-07-21

Applicant: Apple Inc.

Inventor： Douglas C. Holman ,  Ian D. Kountanis ,  Amit Kumar ,  Muawya M. Al-Otoom

IPC: G06F9/30 ,  G06F9/38 ,  G06K9/62

Abstract: Techniques are disclosed relating to signature-based instruction prefetching. In some embodiments, processor pipeline circuitry executes a computer program that includes control transfer instructions, such that the execution follows a taken path through the computer program. First signature prefetch table circuitry indicates prefetch addresses for signatures generated using a first signature generation technique and second signature prefetch table circuitry that indicates prefetch addresses for signatures generated using a second, different signature generation technique. Signature prefetch circuitry, in response to a prefetch training event: determines a first signature according to the first technique and a second signature according to the second technique and selects one but not both of the first and second signature prefetch tables to train using the first signature or the second signature.

公开(公告)号：US11379240B2

公开(公告)日：2022-07-05

申请号：US16778939

申请日：2020-01-31

Applicant: Apple Inc.

Inventor： Muawya M. Al-Otoom ,  Ian D. Kountanis ,  Conrado Blasco ,  Haoyan Jia ,  Amit Kumar

IPC: G06F9/38

Abstract: In an embodiment, an indirect branch predictor generates indirect branch predictions based on one or more register values. The register values may be the contents of registers on which the indirect branch instruction is directly or indirectly dependent for generating the branch target address, for example. In an embodiment, at least one of the registers may be a source for a load instruction, and the indirect branch may be dependent (directly or indirectly) on the target of the load. In an embodiment, the indirect branch predictor may be one of at least two indirect branch predictors in a processor. The other indirect branch predictor may be based on a fetch address, or PC, associated with the indirect branch instruction. The other indirect branch predictor may generate a first predicted target address, and the indirect branch predictor may generate a second predicted target address for the same indirect branch instruction.

公开(公告)号：US10719327B1

公开(公告)日：2020-07-21

申请号：US14716449

申请日：2015-05-19

Applicant: Apple Inc.

Inventor： Muawya M. Al-Otoom ,  Ian D. Kountanis ,  Conrado Blasco

IPC: G06F9/38 ,  G06F9/30

Abstract: In some embodiments, a branch prediction unit includes a plurality of branch prediction circuits and selection logic. At least two of the branch prediction circuits are configured, based on an address of a branch instruction and different sets of history information, to provide a corresponding branch prediction for the branch instruction. At least one storage element of the at least two branch prediction circuits is set associative. The selection logic is configured to select a particular branch prediction output by one of the branch prediction circuits as a current branch prediction output of the branch prediction unit. In some instances, the branch prediction unit may be less likely to replace branch prediction information, as compared to a different branch prediction unit that does not include a set associative storage element. In some embodiments, this arrangement may lead to increased performance of the branch prediction unit.

公开(公告)号：US10346309B1

公开(公告)日：2019-07-09

申请号：US15497338

申请日：2017-04-26

Applicant: Apple Inc.

Inventor： James R. Hakewill ,  Ian D. Kountanis ,  Douglas C. Holman

IPC: G06F12/0811 ,  G06F12/0862 ,  G06F12/0875

Abstract: In an embodiment, a prefetch circuit may implement prefetch “boosting” to reduce the cost of cold (compulsory) misses and thus potentially improve performance. When a demand miss occurs, the prefetch circuit may generate one or more prefetch requests. The prefetch circuit may monitor the progress of the demand miss (and optionally the previously-generated prefetch requests as well) through the cache hierarchy to memory. At various progress points, if the demand miss remains a miss, additional prefetch requests may be launched. For example, if the demand miss accesses a lower level cache and misses, additional prefetch requests may be launched because the latency avoided in prefetching the additional cache blocks is higher, which may over ride the potential that the additional cache blocks are incorrectly prefetched.

公开(公告)号：US20230010948A1

公开(公告)日：2023-01-12

申请号：US17932883

申请日：2022-09-16

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion ,  Ian D. Kountanis ,  Conrado Blasco ,  Steven Andrew Myers ,  Yannick L. Sierra

IPC: G06F9/38 ,  G06F21/60 ,  G06F9/455 ,  G06F9/30

Abstract: A system and method for efficiently protecting branch prediction information. In various embodiments, a computing system includes at least one processor with a branch predictor storing branch target addresses and security tags in a table. The security tag includes one or more components of machine context. When the branch predictor receives a portion of a first program counter of a first branch instruction, and hits on a first table entry during an access, the branch predictor reads out a first security tag. The branch predictor compares one or more components of machine context of the first security tag to one or more components of machine context of the first branch instruction. When there is at least one mismatch, the branch prediction information of the first table entry is not used. Additionally, there is no updating of any branch prediction training information of the first table entry.

公开(公告)号：US11294684B2

公开(公告)日：2022-04-05

申请号：US16778913

申请日：2020-01-31

Applicant: Apple Inc.

Inventor： Ian D. Kountanis

IPC: G06F9/38 ,  G06F9/30

Abstract: In an embodiment, an indirect branch predictor generates indirect branch predictions for indirect branch instructions. For relatively static branch instructions, the indirect branch predictor may be configured to use a PC corresponding to the indirect branch instruction to generate a target prediction. The indirect branch predictor may be configured to identify at least one dynamic indirect branch instruction and may use a different PC than the PC corresponding to the indirect branch instruction to generate the target prediction (e.g. the most recent previous PC associated with a taken branch (“the previous taken PC”). For some dynamic indirect branch instructions, the previous taken PC may disambiguate different target addresses (e.g. there may be a correlation between the previous taken PC and the target address of the indirect branch instruction).

公开(公告)号：US20210240476A1

公开(公告)日：2021-08-05

申请号：US16778913

申请日：2020-01-31

Applicant: Apple Inc.

Inventor： Ian D. Kountanis

IPC: G06F9/38 ,  G06F9/30

Abstract: In an embodiment, an indirect branch predictor generates indirect branch predictions for indirect branch instructions. For relatively static branch instructions, the indirect branch predictor may be configured to use a PC corresponding to the indirect branch instruction to generate a target prediction. The indirect branch predictor may be configured to identify at least one dynamic indirect branch instruction and may use a different PC than the PC corresponding to the indirect branch instruction to generate the target prediction (e.g. the most recent previous PC associated with a taken branch (“the previous taken PC”). For some dynamic indirect branch instructions, the previous taken PC may disambiguate different target addresses (e.g. there may be a correlation between the previous taken PC and the target address of the indirect branch instruction).